Multi-Level Semiconductor Electrodes for Parasitic Capacitance Reduction
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Solution Overview
Problem
Conventional semiconductor devices face challenges in reducing parasitic capacitance and size while maintaining high-frequency power gain, as the reduction in size increases parasitic capacitance between electrodes, making it difficult to achieve both high-frequency operation and efficient heat dissipation.
Innovation Solution
A semiconductor device with electrodes of three or more levels, where the gate drawing electrode is surrounded by grounded source electrodes, reducing feedback of output power and allowing for a smaller device size without compromising high-frequency power gain, even with plastic mold or chip-size packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the device size is reduced, then the cost and complexity decrease, but the parasitic capacitance between electrodes increases
Solution Approach 1:
The patent transitions from planar electrode arrangement to a three-dimensional stacked configuration. The gate electrode is positioned above the drain electrode with vertical separation, creating spatial isolation in the height dimension. This dimensional change allows reduced device footprint while maintaining adequate electrode spacing to control parasitic capacitance.
Solution Approach 2:
The patent implements a nested electrode structure where the gate electrode is surrounded by grounded shield electrodes at multiple levels. The shield electrodes are positioned above and below the gate electrode, creating a nested configuration that shields the gate from drain electric fields while occupying minimal horizontal space.
2Area of stationary object
If the distance between gate electrode, drain electrode, and source electrode is reduced, then the device area decreases, but the parasitic capacitance between electrodes increases
Solution Approach 1:
The patent resolves the area-capacitance tradeoff by moving electrode interactions into the vertical dimension. The gate electrode is separated from the drain electrode by vertical distance rather than horizontal distance, allowing compact planar footprint while maintaining electrical isolation through the height dimension.
Solution Approach 2:
Grounded shield electrodes are introduced as intermediary elements between the gate electrode and drain electrode. These shield electrodes, positioned at multiple levels, intercept and redirect electric field lines to ground, preventing direct capacitive coupling between gate and drain while occupying minimal space.
3Reliability
If a shield electrode is added to reduce parasitic capacitance, then the high-frequency characteristic improves, but the device complexity increases
Solution Approach 1:
The patent combines multiple shield electrode functions into a unified multi-level shielding structure. The shield electrodes at different levels are all grounded and work together as an integrated shielding system, reducing gate-to-drain capacitance through collective action rather than requiring separate complex shielding mechanisms for each interface.
Solution Approach 2:
The shield electrodes are arranged in a nested configuration around the gate electrode, with shields at upper and lower levels creating a compact cylindrical-like shielding structure. This nested arrangement provides effective electromagnetic shielding while minimizing the horizontal space required and simplifying the overall layout.
4Reliability
If the source region area is increased to reduce source resistance, then the source resistance decreases, but the device size increases
Solution Approach 1:
The patent extends the source electrode into the vertical dimension, creating a multi-level source electrode structure that provides low-resistance current paths both horizontally and vertically. This three-dimensional source electrode configuration achieves low source resistance without requiring proportional increases in planar source region area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents a decrease in high-frequency power gain and allows for a reduction in device size, improving high-frequency characteristics and heat dissipation capacity.
Implementation Method 1
a gate drawing electrode is disposed between source electrodes at a first level to reduce a gate resistance so as to improve a high-frequency operation. Furthermore, a shield electrode grounded to a source at a second level shields a gate electrode from a drain electrode to reduce the capacitance of the gate electrode
Implementation Method 2
When a conventional semiconductor device has been further reduced in size, distances between a gate electrode, a drain electrode, and a source electrode decrease to increase parasitic capacitances between the electrodes
Data Source
AI summary
A semiconductor device having electrodes of three or more levels, includes: a semiconductor substrate; an epitaxial layer formed on the semiconductor substrate; a transistor formed on the epitaxial layer; a source electrode formed on the epitaxial layer and electrically connected to a source of the transistor; and a gate drawing electrode formed on the epitaxial layer and electrically connected to a gate of the transistor, wherein the source electrode includes a first source electrode, a second source electrode which is an electrode at a second or higher level on the first source electrode, and a third source electrode which is an electrode at a third or higher level on the second source electrode and above the gate drawing electrode, and the gate drawing electrode is an electrode at a second or higher level on the first source electrode and surrounded with the first, second, and third source electrodes.