Electromigration Resistant Semiconductor Device With Segmented Voltage Rails

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Solution Overview

Problem

Semiconductor devices are susceptible to electromigration, which can lead to open circuits due to void formation and short circuits due to ion/atom accumulation, posing challenges in maintaining the reliability of integrated circuits like ASICs.

Innovation Solution

Incorporating a header with a pair of virtual source reference rails and a footer with a pair of virtual reference voltage rails, connected by a cell circuit, which disperses current and reduces current density, thereby mitigating electromigration through the use of transistor units and via units to manage voltage rails effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional standard cell layouts are used, then device complexity is reduced and manufacturing is easier, but electromigration resistance deteriorates leading to circuit failures

Engineering Contradiction:
Improveelectromigration resistanceVSAvoidcell structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The voltage rail is segmented into multiple parallel rails (first voltage rail, second voltage rail, third voltage rail) instead of using a single rail. This segmentation distributes the current across multiple paths, reducing current density in each individual rail and thereby improving electromigration resistance while maintaining a structured and manageable cell design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A fourth voltage rail is introduced as an intermediary element coupled to the first, second, and third voltage rails. This intermediate rail helps balance voltages across the segmented structure and provides additional current distribution paths, further enhancing electromigration resistance without significantly increasing overall device complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If current is concentrated in single voltage rails, then device structure is simpler, but current density increases causing electromigration and void formation

Engineering Contradiction:
Improveelectromigration resistanceVSAvoidvoltage rail configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The voltage distribution network is divided into multiple parallel voltage rails (first, second, and third voltage rails) that carry current simultaneously. This segmentation reduces the current burden on each individual rail, lowering current density and preventing electromigration-related failures such as void formation and ion accumulation

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple voltage rails are combined in parallel to form a unified voltage distribution system. The fourth voltage rail acts as a common intermediary that connects and balances the other three rails, creating a merged structure that distributes current more evenly and improves overall electromigration resistance

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10128234B2Electromigration resistant semiconductor device
Publication Date: 2018.11.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10128234B2 patent drawing
  • US10128234B2 patent drawing
  • US10128234B2 patent drawing

AI summary

A semiconductor device includes first and second transistors, a pair of first source/drain regions, a pair of second source/drain regions, and a cell. Each of the first source/drain regions corresponds to a first source/drain terminal of a respective one of the first and second transistors. Each of the second source/drain regions corresponds to a second source/drain terminal of a respective one of the first and second transistors. The cell includes a first voltage rail, a pair of second voltage rails, and a cell circuit. The first voltage rail is coupled to the first source/drain regions. Each of the second voltage rails is coupled to a respective one of the second source/drain regions and is configured to be coupled to the first voltage rail. The cell circuit is coupled to one of the second voltage rails.