Semiconductor Memory Cell Electron Trap Layer Design
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Solution Overview
Problem
In semiconductor devices, particularly flash memory devices, the challenge lies in preventing electrons injected into the floating gate from being discharged to the control gate during program operations, which affects the memory cell's threshold voltage and data retention, especially as chip sizes decrease and memory cell spacing narrows.
Innovation Solution
The semiconductor device employs an electron injection operation that traps electrons in the inter-poly dielectric, rather than allowing them to flow to the control gate, by controlling voltage differences and application intervals to prevent electron leakage, thereby enhancing operation characteristics and data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high program voltage is supplied to control gates of memory cells, then electrons are injected into the floating gate for data storage, but electrons are discharged to the control gate through the inter-poly dielectric causing threshold voltage degradation
Solution Approach 1:
An electron trap layer is introduced between the inter-poly dielectric and the control gate to act as an intermediary. This trap layer captures electrons that would otherwise leak into the control gate, preventing threshold voltage degradation while allowing the program operation to proceed effectively
Solution Approach 2:
The patent converts the harmful electron leakage phenomenon into a beneficial effect by utilizing the trap layer to deliberately capture these electrons. The electrons that would cause damage are instead used to fill trap states in a controlled manner, improving device reliability
2Area of stationary object
If chip size is reduced and memory cell spacing is narrowed, then device integration is improved, but electron leakage from floating gate to control gate increases
Solution Approach 1:
The electron trap layer serves as a protective intermediary that becomes increasingly important as cell spacing decreases. It intercepts electrons before they can traverse the narrowed path to the control gate, enabling continued scaling without proportionally increasing leakage
Solution Approach 2:
The dielectric structure between the floating gate and control gate is segmented into multiple functional layers: the inter-poly dielectric for electrical isolation and the electron trap layer for electron capture. This segmentation allows each layer to perform its specific function optimally
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents electron leakage, increases the threshold voltage of memory cells, and improves data retention by trapping electrons in the inter-poly dielectric, ensuring stable operation and enhanced performance in reduced chip sizes.
Implementation Method 1
performing an electron injection operation of trapping electrons in the inter-poly dielectric of the memory cell
Data Source
AI summary
A semiconductor device includes a memory block coupled to word lines and configured to a memory cell including a floating gate, an inter-poly dielectric and a control gate and a peripheral circuit configured to perform an erase loop operation, a program loop operation an electron injection operation of the memory cell, the electron injection operation trapping electrons in the inter-poly dielectric.