Semiconductor Element Configuration for Reduced Thermal Resistance
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Solution Overview
Problem
Conventional semiconductor devices fail to further reduce thermal resistance due to the long distance between semiconductor elements within the same module, leading to insufficient heat dissipation.
Innovation Solution
The semiconductor device configuration features a narrower voltage applied region on each semiconductor element, with semiconductor elements disposed such that the shortest distance between elements of the same arm is longer than between elements of different arms, reducing thermal interference and enhancing heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If semiconductor elements are disposed with long distance between modules, then thermal resistance is reduced, but device size increases and heat dissipation efficiency decreases
Solution Approach 1:
The patent applies local quality by differentiating the spacing between semiconductor elements based on their functional groups. Elements of the same arm (upper or lower) are positioned closer together, while elements from different arms maintain larger spacing. This localized spacing strategy optimizes thermal resistance without uniformly increasing device size, as the spacing is tailored to specific thermal management needs of each element group.
Solution Approach 2:
The patent employs asymmetry in the spatial arrangement of semiconductor elements. Rather than uniform spacing, the configuration creates asymmetric patterns where distance between elements varies based on their arm affiliation. This asymmetric layout allows thermal paths to be optimized for critical elements while maintaining compact overall device dimensions, resolving the contradiction between thermal resistance reduction and device size control.
2Area of stationary object
If semiconductor elements are disposed closer together, then device size is reduced, but thermal resistance increases and heat dissipation becomes insufficient
Solution Approach 1:
The patent implements local quality by applying different spacing strategies to different semiconductor element groups. Elements requiring better thermal management (same arm elements) are positioned closer, while elements from different arms maintain larger spacing for thermal isolation. This localized differentiation allows the device to achieve compact size without uniformly increasing thermal resistance across all elements.
Solution Approach 2:
The patent segments the semiconductor elements into distinct groups based on their arm affiliation (upper arm vs. lower arm). This segmentation allows independent optimization of spacing for each group, enabling the device to maintain compact overall dimensions while ensuring that critical thermal paths within each segment are optimized. The segmented approach resolves the contradiction by allowing different spacing characteristics in different segments of the device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces thermal resistance and allows for a smaller device size while maintaining efficient heat dissipation, addressing the limitations of conventional designs.
Implementation Method 1
a first semiconductor element (31a, 31b) constituting one arm of upper arms and lower arms and a nearest second semiconductor element (32a, 32b) constituting the one arm is longer than the shortest distance between the first semiconductor element (31a, 31b) and a nearest third semiconductor element (32a, 32b) constituting the other arm
Data Source
AI summary
The semiconductor device includes at least three semiconductor elements disposed directly or indirectly on a planar member and constituting an upper arm and a lower arm which perform ON and OFF action at mutually differential times; an upper-surface voltage applied region of each semiconductor element is configured to be narrower than an area of the aforementioned whole semiconductor element in planar view; and each semiconductor element is disposed so that the shortest distance between the semiconductor elements constituting the upper arm is formed so as to be longer than the shortest distance between the semiconductor element constituting the upper arm and the semiconductor element constituting the lower arm.