Semiconductor Device Embedding Material Side Surface Etching
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Solution Overview
Problem
In DRAM memory devices, the proximity of the side surface of the embedding material to the peripheral circuit region reduces the margin between contact plugs and the embedding material, potentially leading to short-circuiting and defects due to the uneven side surface and level differences between the memory cell array and peripheral circuit regions.
Innovation Solution
The side surface of the embedding material is flattened and slimmed through a combination of isotropic and anisotropic dry etching processes, followed by the formation of an interlayer dielectric film and contact plugs, which increases the margin between the contact plugs and the embedding material, reducing the risk of short-circuiting and defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the side surface of the embedding material is located near the peripheral circuit region to reduce chip size, then the chip size is reduced, but the margin between contact plugs and the embedding material is decreased, increasing the risk of short-circuiting
Solution Approach 1:
The side surface of the embedding material is divided into multiple etching stages: first an isotropic etching process creates a recessed portion, then an anisotropic etching process further shapes the side surface. This segmentation of the etching process allows precise control of the side surface profile to maximize the margin between contact plugs and embedding material while maintaining compact chip dimensions.
Solution Approach 2:
The etching parameters are optimized to achieve the desired side surface profile. By controlling etching depth, etching rate, and etching direction through different etching processes, the side surface is shaped to provide adequate margin for contact plugs. The recessed portion depth and side surface angle are specifically tuned to resolve the contradiction between compact size and sufficient margin.
2Ease of manufacture
If the side surface of the embedding material is uneven due to level differences between memory cell array and peripheral circuit regions, then the manufacturing process is simplified, but short-circuiting and defects occur due to reduced margin
Solution Approach 1:
The side surface formation is segmented into two distinct etching processes: isotropic etching followed by anisotropic etching. This segmentation allows the first process to handle the uneven level differences between regions, while the second process precisely shapes the side surface to prevent short-circuiting, thus maintaining both manufacturing ease and reliability.
Solution Approach 2:
The recessed portion formed by isotropic etching acts as an intermediary structure that accommodates the level differences between memory cell array and peripheral circuit regions. This intermediate feature allows subsequent anisotropic etching to create a properly shaped side surface, bridging the gap between manufacturing simplicity and electrical reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of the semiconductor device by increasing the margin between contact plugs and the embedding material, reducing chip size, and minimizing seams and defects in the interlayer dielectric film, thereby improving the overall manufacturing process and device performance.
Implementation Method 1
The side surface of the embedding material is flattened and slimmed through a combination of isotropic and anisotropic dry etching processes
Data Source
AI summary
Disclosed herein is an apparatus that includes a plurality of cell capacitors arranged in a memory cell array region of a semiconductor substrate, each of the plurality of cell capacitors having a first electrode, a second electrode and an insulating film therebetween to electrically disconnect the first and second electrodes, a first conductive member including the plurality of cell capacitors therein, the first conductive member being electrically connected in common to the first electrodes of the plurality of cell capacitors, and a second conductive member formed on an upper surface of the first conductive member, a material of the second conductive member being different from that of the first conductive member. A side surface of the first conductive member is free from the second conductive member.