Semiconductor Emitter Electrode Flatness via Non-Overlapping Holes
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Solution Overview
Problem
Conventional semiconductor devices with discrete bipolar transistors experience non-uniform current density due to higher resistance in long current paths, leading to thermal runaway and reduced safety operation area (ASO), and activation failures of cells, which increase resistance components and non-uniformity.
Innovation Solution
The semiconductor device design includes a second emitter electrode with an increased area and a metal plate for external connection, where the emitter contact holes and through holes are arranged to prevent overlap, improving the flatness of the second emitter electrode's surface and reducing level differences, allowing for better solder wettability and fixation of the metal plate, and optimizing current paths for uniform current density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional two-layer electrode structure is used, then device complexity is reduced, but current density becomes non-uniform leading to thermal runaway
Solution Approach 1:
The electrode structure is divided into multiple layers (first layer with island-like and stripe-like electrodes, second layer with plate-like electrodes) to segment current paths. This segmentation creates multiple parallel current flow routes, distributing current density uniformly across the device and preventing thermal runaway.
Solution Approach 2:
The invention transitions from a conventional planar electrode layout to a three-dimensional multi-layer structure. By stacking electrodes in different layers with through-holes connecting them, current can flow through multiple spatial dimensions, creating more uniform current distribution throughout the volume of the device.
2Manufacturing precision
If emitter contact holes and through holes overlap, then area is reduced, but surface flatness deteriorates and solder wettability is poor
Solution Approach 1:
Instead of arranging contact holes and through-holes in the same plane (2D overlap), the invention uses the vertical dimension (3D stacking) to separate them. Emitter contact holes are formed in the first insulating film, while through-holes are formed in the second insulating film at different locations, eliminating overlap and ensuring surface flatness for good solder wettability.
3Productivity
If chip size is reduced, then productivity is improved, but maintaining ASO size and resistance values becomes difficult
Solution Approach 1:
The multi-layer electrode structure utilizes the vertical dimension to increase effective electrode area without increasing chip footprint. Through-holes and stacked electrodes provide additional current paths in the depth direction, maintaining low resistance and safe operating area while reducing the horizontal chip dimensions.
Solution Approach 2:
The electrode structure employs nested configurations where second layer plate-like electrodes are positioned to overlay and connect with first layer island-like and stripe-like electrodes through through-holes. This nesting creates compact, space-efficient current paths that maintain electrical performance in a reduced chip area.
Data Source
AI summary
Emitter contact holes formed under emitter electrodes in a first layer and emitter through holes formed thereon are arranged so as not to overlap each other, and, for each emitter electrode, the multiple emitter contact holes and the multiple emitter through holes are provided so as to be separated from each other. Thereby, the top surface of an emitter electrode in a second layer is influenced by at most only a level difference of each emitter through hole formed in an insulating film having a larger thickness, and thus the flatness of the top surface of the emitter electrode in the second layer is improved. Accordingly, fixation failure of a metal plate can be avoided.