Semiconductor Structure with Engineered Insulating Substrate
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Solution Overview
Problem
Current semiconductor substrates for RF applications, such as Silicon on Insulators (SOI) and Silicon-on-Sapphire (SOS), face issues like significant substrate loss, high cost, and low thermal conductivity, making them unsuitable for large-scale and cost-effective RF applications.
Innovation Solution
A semiconductor structure featuring an insulating substrate surrounded by an engineered layer comprising aluminum nitride, polycrystalline silicon carbide, or polycrystalline diamond, with a specific configuration of oxide and nitride layers to minimize substrate loss and enhance thermal conductivity, along with a fabrication method that includes forming gate and source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If Silicon on Insulators (SOI) is used for RF applications, then substrate loss is reduced, but cost increases and special processes are required
Solution Approach 1:
The patent segments the substrate structure into distinct functional layers: a bulk substrate providing mechanical support and thermal conduction, an insulating layer providing electrical isolation, and a semiconductor layer for device fabrication. This segmentation allows each layer to be optimized independently, reducing substrate loss while avoiding the need for expensive SOI wafers.
Solution Approach 2:
The patent employs a composite substrate structure combining different materials: a semiconductor substrate (e.g., silicon) for thermal conduction and mechanical strength, an insulating material (e.g., silicon dioxide or silicon nitride) for electrical isolation, and a buffer layer for stress management. This composite approach achieves low substrate loss and high thermal conductivity without the cost and process complexity of SOI.
2Loss of energy
If Silicon-on-Sapphire (SOS) is used for RF applications, then substrate loss is reduced, but thermal conductivity decreases and cost increases
Solution Approach 1:
The patent applies local quality by providing thermal conduction only where needed: the bulk substrate maintains high thermal conductivity in the vertical direction to dissipate heat from active devices, while the insulating layer provides electrical isolation horizontally. This localized approach to thermal and electrical management reduces substrate loss without compromising thermal conductivity.
Solution Approach 2:
The patent uses a composite structure with a high thermal conductivity substrate (e.g., silicon or silicon carbide) combined with a thin insulating layer. This composite maintains excellent thermal conduction pathways while providing necessary electrical isolation, avoiding the low thermal conductivity problem of sapphire substrates.
3Ease of manufacture
If heteroepitaxial growth is used for SOS, then device fabrication is enabled, but substrate scaling to large diameters is limited
Solution Approach 1:
The patent creates a universal substrate structure that works for both small and large diameter substrates. The combination of bulk substrate, insulating layer, and semiconductor layer can be fabricated on standard large-diameter silicon or silicon carbide wafers using conventional epitaxial growth, enabling device fabrication without the substrate size limitations of SOS.
Data Source
AI summary
A semiconductor structure includes an insulating substrate, an engineered layer, a semiconductor layer, and an isolation structure. The engineered layer is surrounding the insulating substrate. The semiconductor layer, which includes a first region and a second region,. is formed over the engineered layer. The isolation structure is formed in the semiconductor layer and located between the first region and the second region. A first transistor and a second transistor are formed in the first region and the second region respectively.