Semiconductor Device Epitaxial Layer Spacer Wall Design
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Solution Overview
Problem
Current semiconductor devices using embedded silicon germanium (SiGe) processes face limitations in enhancing performance due to the need for improved stress application and hole mobility in the channel region.
Innovation Solution
A semiconductor device design featuring a substrate with a gate structure, source/drain region, epitaxial layer, and spacer wall, where the source/drain region is partially embedded in the substrate with a diamond-shaped cross-section, and an epitaxial layer is introduced between the gate structure and source/drain region to increase overall height and reduce the distance to the channel region, enhancing stress application and hole mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the distance between source/drain region and channel region is reduced to enhance stress application, then hole mobility and operating speed improve, but manufacturing precision requirements increase
Solution Approach 1:
The tip of the source/drain region is pre-formed to extend into the substrate at a predetermined position and depth before final device assembly. This preliminary positioning establishes the optimal distance to the channel region in advance, ensuring precise stress application without requiring complex real-time adjustments during manufacturing, thus maintaining high manufacturing precision while achieving improved operating speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively improves stress application and hole mobility, leading to enhanced semiconductor device performance by decreasing the distance between the source/drain region and the channel region, thereby increasing the operating speed and performance.
Implementation Method 1
an epitaxial layer is introduced between the gate structure and source/drain region to increase overall height and reduce the distance to the channel region
Data Source
AI summary
A manufacturing method of a semiconductor device at least includes the following steps. A substrate having a stacked structure is provided. An epitaxy process is performed to form an epitaxial layer on the substrate on two sides of the stacked structure. A recess is forming on the two sides of the stacked structure, wherein the recess penetrates through the epitaxial layer, extends into the substrate, and has a tip located in the substrate. A source/drain region is formed in the recess, wherein a material of the source/drain region comprises silicon germanium. A spacer wall material layer is formed on the substrate. A portion of the stacked structure is removed to from a gate structure. A portion of the spacer wall material layer is removed to form a spacer wall on the epitaxial layer. A semiconductor device is also provided.