Semiconductor Integrated Circuit Erase Area Detection
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Solution Overview
Problem
Conventional semiconductor memory systems experience read disturb and increased latency due to the need for retry operations to detect whether an erase area is accessed during read errors, which lowers reliability and degrades access performance.
Innovation Solution
Incorporating an erase area detecting-circuit that recognizes the bit state of data read from nonvolatile semiconductor memory by a frame size unit, allowing for the detection of erase areas during the initial read operation without retrying, thereby improving reliability and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a retry operation is executed to detect whether an erase area is accessed when a read error occurs, then the reliability is improved by correctly identifying erase areas, but the latency is deteriorated and read disturb is encouraged
Solution Approach 1:
The patent applies preliminary action by performing erase area detection during the initial read operation before any retry operation is executed. The detection circuit monitors bit states of read data in real-time and identifies erase areas proactively, eliminating the need for subsequent retry operations and reducing latency while maintaining reliability
2Reliability
If a retry operation is executed to detect whether an erase area is accessed, then the reliability is improved, but the number of read operations increases causing read disturb
Solution Approach 1:
The detection circuit performs erase area identification during the first read operation by monitoring bit states of read data. This preliminary detection prevents the need for retry operations that would cause additional read disturbances, thereby improving reliability without increasing read disturb
3Measurement precision
If conventional read error processing is used, then the system can detect read errors, but the processing complexity increases due to multiple processing steps
Solution Approach 1:
The patent merges the erase area detection function with the existing read error processing circuitry. The detection circuit is integrated into the read operation flow, combining error detection and erase area identification into a unified processing path, thereby reducing overall processing complexity while maintaining detection precision
Solution Approach 2:
By performing erase area detection during the initial read operation before error processing begins, the patent eliminates subsequent retry operations and simplifies the overall processing flow. The detection circuit provides early identification of erase areas, reducing the number of processing steps required
Data Source
AI summary
According to one embodiment, a semiconductor integrated circuit includes an input register which latches, by a second unit, data which are read from a memory cell array by a first unit, a bit state-counter which counts a bit state of the data latched in the input register, a frame size-setup register which latches the first unit, an input data-counter which detects whether or not a total number of the data input to the input register reaches to the first unit, an accumulation circuit which accumulate a value counted by the bit state-counter, a threshold value-register which latches a threshold value for detecting whether or not an erase area of the memory cell array is accessed, a comparison circuit which compares an accumulated value of the accumulation circuit and the threshold value with each other, and a product storage-register which latches a result of the comparison circuit.