Semiconductor Device Erase Level Control for NAND Memory
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Solution Overview
Problem
NAND memory devices experience significant interference during program operations due to broad voltage distribution widths of threshold voltages in memory cells after an erase operation, leading to deteriorated data storage characteristics.
Innovation Solution
A semiconductor device with a memory block that groups word lines into different groups based on proximity to bit lines and common source lines, allowing for controlled erase levels, where memory cells closer to bit lines and common source lines are distributed at distinct erase levels, enabling improved program operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an erase operation is performed on the memory block, then the threshold voltages of memory cells are reset to an erase level, but the threshold voltages exhibit broad voltage distribution width causing significant interference during subsequent program operations
Solution Approach 1:
The patent segments the memory block into two distinct groups: first memory cells closer to the common source line and second memory cells closer to the bit line. Different erase levels are applied to each segment, allowing tailored voltage control for each group and reducing overall threshold voltage distribution width.
Solution Approach 2:
Different erase levels are assigned to different spatial locations within the memory block. First memory cells receive a first erase level while second memory cells receive a second erase level, optimizing the threshold voltage characteristics for each local region based on its specific electrical environment.
2Ease of operation
If threshold voltages of memory cells are distributed at the same erase level, then the erase operation is simplified, but significant interference occurs during program operations due to broad voltage distribution
Solution Approach 1:
The memory block is divided into two segments (first and second memory cells) that are processed differently during the erase operation. This segmentation allows the system to reduce interference during program operations while maintaining reasonable operational complexity through automated control.
Solution Approach 2:
The erase level parameter is changed from a single uniform value to two distinct values (first erase level and second erase level) applied to different memory cell groups. This parameter differentiation reduces the broad voltage distribution that causes interference during program operations.
3Manufacturing precision
If different erase levels are applied to memory cells closer to bit lines and common source line, then threshold voltage distribution width is reduced, but the erase operation complexity increases
Solution Approach 1:
The control block automatically segments memory cells into two groups based on their physical location (closer to common source line vs. closer to bit line). This segmentation enables precise threshold voltage control for each group while the control logic handles the complexity of applying different erase levels.
Solution Approach 2:
The control block acts as an intermediary that manages the complexity of applying different erase levels. It automatically determines which memory cells receive which erase level based on their location, shielding the user from the operational complexity while achieving precise threshold voltage distribution control.
Data Source
AI summary
A semiconductor device includes a memory block including memory cells coupled between bit lines and a common source line and operated by voltages applied to word lines, and an operation control block suitable for performing an erase operation and a pre-program operation on the memory block, wherein the operation control block performs an erase level control operation after the erase operation is completed so that threshold voltages of the memory cells relatively close to the bit lines and threshold voltages of the memory cells relatively close to the common source line are distributed at different erase levels.