Semiconductor Device Erase Stress Reduction via Local Word Line Control
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Solution Overview
Problem
Semiconductor memory devices face stress issues during erase operations, particularly affecting non-selected memory blocks and row decoders, which can lead to reduced integration and performance.
Innovation Solution
The solution involves grounding local word lines connected to non-selected memory blocks and applying a pre-erase voltage lower than the erase voltage to the source line, while floating these word lines to prevent voltage increase and reduce stress on non-selected memory blocks during the erase operation of a selected memory block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase voltage is applied to the source line during erase operation, then the erase operation of the selected memory block is performed, but voltage increases on non-selected memory blocks causing stress and potential breakdown
Solution Approach 1:
The patent applies preliminary anti-action by grounding the local word lines connected to non-selected memory blocks before applying the erase voltage to the source line. This pre-grounding action creates a reference potential that prevents voltage increase on the non-selected memory blocks during the erase operation, thereby reducing stress and protecting against breakdown.
Solution Approach 2:
The patent implements preliminary action by first applying a pre-erase voltage (lower than the full erase voltage) to the source line, and only after this preliminary voltage is established does it apply the full erase voltage. This staged approach allows the system to prepare the electrical environment before subjecting non-selected blocks to full stress conditions.
2Device complexity
If local word lines are kept floating during erase operation, then simple control is maintained, but voltage increases causing stress on non-selected memory blocks
Solution Approach 1:
The patent applies segmentation by dividing the word line control into two distinct groups: local word lines connected to non-selected memory blocks (which are grounded to prevent voltage increase) and local word lines connected to the selected memory block (which remain floating or are controlled differently). This segmented control strategy manages voltage distribution effectively without requiring complex global control mechanisms.
Data Source
AI summary
Disclosed are a semiconductor device and an operating method thereof. The semiconductor device includes a plurality of memory blocks including cell strings coupled between bit lines and a source line, a peripheral circuit configured to perform an erase operation on a selected memory block among the plurality of memory blocks; and a control circuit configured to control the peripheral circuit, so that when an erase command is received, local word lines coupled to a non-selected memory block among the plurality of memory blocks are pulled to ground, the local word lines coupled to the non-selected memory block float after a pre-erase voltage lower than an erase voltage is applied to the source line, and the erase operation of the selected memory block is performed by applying the erase voltage to the source line.