Semiconductor Error Check and Scrub Circuit for DDR Memory
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Solution Overview
Problem
As data transmission speeds in semiconductor devices increase, so does the likelihood of errors, necessitating advanced error correction mechanisms to ensure reliable data transmission, particularly in DDR2 and DDR3 schemes.
Innovation Solution
A semiconductor device incorporating an error check and scrub (ECS) command generation circuit and ECS control circuit that generates ECS commands, activates ECS mode signals, and performs ECS operations to detect and correct errors in memory cells, while also logging error information for row paths with maximum errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission speed is increased to improve operation speed, then productivity is improved, but error occurrence probability increases
Solution Approach 1:
The patent implements preliminary error detection and correction by generating ECS commands during refresh operations before errors can propagate. The error check and scrub circuit performs error detection and correction in advance during memory refresh cycles, preventing errors from affecting normal high-speed data transmission operations.
Solution Approach 2:
The memory device performs self-diagnosis and self-correction by automatically executing ECS operations using internally generated commands. The error check and scrub circuit autonomously detects and corrects errors without external intervention, allowing the system to maintain high-speed operation while ensuring data reliability through automatic error handling.
2Reliability
If error correction mechanisms are added to improve data transmission reliability, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges error correction functionality with the existing refresh operation by generating ECS commands based on refresh commands. The error check and scrub circuit is integrated into the command decoding structure, combining error detection/correction functions with normal memory refresh operations to reduce overall system complexity.
Solution Approach 2:
The refresh command structure is given multi-functionality by using it to generate both normal refresh operations and error correction operations. The same command decoding circuitry handles both refresh and ECS command generation, allowing a single mechanism to serve multiple purposes and reducing the need for separate dedicated error correction hardware.
3Reliability
If ECS operations are performed continuously to detect and correct errors, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic error correction by triggering ECS operations during scheduled refresh cycles rather than continuously. The ECS command generation circuit generates correction commands at specific intervals based on refresh command timing, ensuring errors are corrected regularly while allowing the system to consume less power during non-ECS periods.
Solution Approach 2:
The error correction function is continuously available by integrating it into the refresh operation framework. Since refresh operations must occur periodically anyway to maintain memory data integrity, the error correction action continues alongside these necessary refresh cycles without requiring additional dedicated correction operations, thus maintaining reliability while managing power consumption efficiently.
Data Source
AI summary
A semiconductor device includes an error check and scrub (ECS) command generation circuit and an ECS control circuit. The ECS command generation circuit generates an ECS command based on a refresh command. During an ECS operation, the ECS control circuit generates an ECS mode signal that is activated based on the ECS command and generates an ECS active command, an ECS read command, and an ECS write command to continue the ECS operation.