Semiconductor Error Check Signal Disable Mechanism

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Solution Overview

Problem

As semiconductor devices operate at faster data transmission speeds, the probability of error occurrence increases, necessitating advanced design techniques for reliable data transmission, including the use of error codes like cyclic redundancy checks and error correction codes, but existing systems lack efficient mechanisms to manage error detection and correction in high-error scenarios.

Innovation Solution

A semiconductor system is designed with multiple devices that perform independent error check operations based on error check enablement signals and clock signals, generating error check signals that are disabled after a predetermined number of error occurrences, thereby preventing further error check operations and maintaining data transmission reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data transmission speed is increased to improve operation speed, then productivity is improved, but error occurrence probability increases

Engineering Contradiction:
Improveoperation speedVSAvoiddata transmission reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where error check circuits continuously monitor data transmission and provide feedback signals to the controller. When errors are detected, the system adjusts its operation by disabling error check operations after a predetermined number of error occurrences, thereby resolving the contradiction between high-speed operation and reliable data transmission.

Inventive Principle:
Principle #23Feedback

2Reliability

If error check operations are continuously performed to improve data transmission reliability, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoiderror check system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies dynamics by making the error check operation configurable and adaptable. The system dynamically adjusts error check behavior based on error occurrence patterns, disabling further error check operations after a predetermined number of errors. This dynamic approach maintains reliability while avoiding the complexity of continuously performing error checks in all scenarios.

Inventive Principle:
Principle #15Dynamics

3Reliability

If error check operations are disabled after predetermined error occurrences to prevent further errors, then reliability is maintained, but loss of information increases

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoiddata transmission continuity
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The patent implements beforehand cushioning by establishing a threshold of predetermined error occurrences before disabling error check operations. This cushioning approach allows the system to tolerate a certain number of errors while maintaining error check functionality, and only disables operations when the error rate exceeds the predetermined threshold, thus balancing reliability maintenance with information loss prevention.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS11309046B2Semiconductor devices and semiconductor systems including the same
Publication Date: 2022.04.19 SK HYNIX INC
  • US11309046B2 patent drawing
  • US11309046B2 patent drawing
  • US11309046B2 patent drawing

AI summary

A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs an error check enablement signal, an input clock signal, and input data to the second semiconductor device. The first semiconductor device receives an error check signal from the second semiconductor device. The second semiconductor device performs an error check operation for the input data based on the error check enablement signal and the input clock signal to generate the error check signal which is enabled when an error in the input data occurs.