Semiconductor Error Code Comparison Circuit for Fast Data Transmission
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Solution Overview
Problem
As semiconductor memory devices with fine patterns of 10 nanometers or less and fast interfaces like DDR4 schemes increase data transmission speeds, the probability of errors also rises, necessitating novel designs for reliable data transmission, where existing error detection and correction methods are inadequate.
Innovation Solution
A semiconductor system comprising a first and second semiconductor device, where the second device includes an error correction circuit that generates and compares error codes during write and read operations, respectively, to detect and correct errors, with the number of bits in the error codes being less than the data, thereby reducing detection time and current requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission speed is increased, then productivity is improved, but error probability increases
Solution Approach 1:
An error correction circuit is introduced as an intermediary component between the data transmission path and the error detection mechanism. This circuit generates error codes that serve as mediators to detect and correct errors without requiring retransmission, thus maintaining high transmission speeds while improving reliability
Solution Approach 2:
Instead of copying and comparing entire data sets, the system generates compact error codes that represent the error state of the data. These error codes are copies of error information rather than full data copies, enabling fast comparison with minimal overhead to the transmission speed
2Loss of time
If error codes with fewer bits are used, then detection time is reduced, but error detection capability may be compromised
Solution Approach 1:
The system changes the parameter of error code length to be fewer bits than traditional ECC codes. By optimizing the error code length to match the specific error detection needs rather than using fixed-length codes, the system achieves faster detection while maintaining adequate error detection capability for the application
Solution Approach 2:
The error correction circuit applies different error detection strategies to different parts of the data transmission process. By generating error codes only for portions of data that are prone to errors or require verification, the system reduces overall detection time while maintaining reliability where needed
3Use of energy by moving object
If error codes with fewer bits are used, then current consumption is reduced, but error detection accuracy may decrease
Solution Approach 1:
The system optimizes the bit length parameter of error codes to find the minimum sufficient length that provides adequate error detection accuracy. By changing this parameter from fixed traditional lengths to optimized shorter lengths, the system reduces current consumption while maintaining the necessary detection accuracy
Solution Approach 2:
The error correction circuit extracts only the essential error detection information needed for reliable operation, discarding redundant bits. This extraction process creates compact error codes that consume less current while retaining the core error detection functionality
Data Source
AI summary
A semiconductor device and or system may be provided. The semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a command/address signal, a first datum and a second datum. The first semiconductor device may be configured to receive a comparison signal relating to the first datum and the second datum. The second semiconductor device may be configured to store a first error code of the first datum and a second error code of the second datum based on the command/address signal during a write operation. The second semiconductor device may be configured to compare the first error code with the second error code to output the comparison signal based on the command/address signal during a read operation.