Semiconductor Error Correction Reference Cell Management
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Solution Overview
Problem
In semiconductor memory devices using a reference cell method, reducing the number of reference cells to minimize device size and cost leads to errors in data amplification when a single reference cell is shared among multiple sense amplifiers, exceeding the error correction capability, which affects data reliability.
Innovation Solution
A semiconductor device with a memory cell array comprising first, second, and third memory cells, a judging circuit, and an error detection and correction circuit that uses a reference signal to judge data values and writes reference data to third memory cells when errors exceed the correction capability, preventing further errors in data amplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the number of reference cells is reduced to minimize device size and cost, then device size and cost are reduced, but errors in data amplification occur when a single reference cell is shared among multiple sense amplifiers
Solution Approach 1:
The patent divides the reference cell functionality into multiple segments: first memory cells store original data, third memory cells store reference data, and second memory cells store error correcting codes. This segmentation allows the system to maintain data reliability even when reference cells are reduced, as errors can be detected and corrected through the distributed storage architecture.
Solution Approach 2:
The patent performs preliminary error detection and correction by storing error correcting codes in second memory cells alongside the reference data in third memory cells. This preliminary action enables the system to identify and correct errors before they affect data amplification, maintaining reliability while using fewer reference cells.
2Device complexity
If a single reference cell is shared by multiple sense amplifiers, then device complexity is reduced, but errors exceed the error correction capability
Solution Approach 1:
The patent introduces second memory cells as intermediary elements that store error correcting codes. These intermediaries enable the system to maintain error correction capability even when reference cells are shared, as the error correcting codes provide an additional layer of protection against amplification errors.
Solution Approach 2:
The patent changes the parameters of the memory system by introducing a three-type memory cell architecture with different functions. First memory cells hold original data, third memory cells hold reference data, and second memory cells hold error correcting codes. This parameter change enables the system to maintain reliability while reducing reference cell count.
3Reliability
If error correction is performed continuously, then data reliability is maintained, but power consumption increases
Solution Approach 1:
The patent implements periodic error correction by performing judgment and correction operations only when necessary, rather than continuously. The error detection and correction circuit activates based on detected errors, reducing unnecessary write operations and power consumption while maintaining data reliability when errors occur.
Data Source
AI summary
A device with error correction is provided. The device includes a plurality of memory cells, and reference read write circuit, a plurality of sense amplifiers, and an error-correction code control block. The reference read write circuit is configured to generate a reference voltage in response to data stored in at least one of the plurality of memory cells. A plurality of sense amplifiers are each coupled to a respective memory cell of the plurality of memory cells. An error-correction code (ECC) control block may output an error signal when the ECC control block detects that it is unable to correct error data in one or more respective memory cells. The reference read write circuit may overwrite data in the at least one of the plurality of memory cells in response to the error signal.