Semiconductor Error Detection Circuit for Parallel Burst Chop
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Solution Overview
Problem
As semiconductor devices increase operating speed by inputting/outputting multiple data in each clock cycle, the probability of errors during data transmission also rises, necessitating a separate device and method to ensure data transmission reliability, which existing error code methods like CRC, EDC, and ECC do not adequately address.
Innovation Solution
A semiconductor device that includes an error detection circuit to generate an error detection signal by fixing internal data to a preset level based on a burst chop signal and internal command address during a read operation, and a data output circuit to serialize internal data and the error detection signal after a read latency period, enabling parallel burst chop and error check operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission speed is increased by inputting/outputting multiple data in each clock cycle, then productivity is improved, but reliability deteriorates due to increased error probability
Solution Approach 1:
The patent merges the burst chop operation and error check operation into a single integrated process. The error check control circuit performs error detection on internal data while the data is being prepared for output during the burst chop operation, combining two previously separate functions into one concurrent process. This allows error checking to occur without adding extra time or cycles to the data transmission process.
Solution Approach 2:
The error detection is performed in advance during the read latency period before the data is actually output. The error check control circuit generates the error detection signal by processing internal data while it is still being prepared, so that when the data is finally output, the error status is already determined and can be transmitted alongside the data without delaying the overall process.
2Reliability
If a separate error checking device and method are added to ensure data transmission reliability, then reliability is improved, but device complexity increases
Solution Approach 1:
The error check control circuit is integrated within the existing memory device architecture, sharing resources with the burst chop control logic. The same control signals and data paths are utilized for both burst chop operations and error checking, eliminating the need for completely separate error checking hardware and reducing overall device complexity.
Solution Approach 2:
The error check control circuit is designed to perform multiple functions: it controls the burst chop operation, manages the read latency timing, generates error detection signals, and coordinates the output of both data and error signals. This multi-functional approach eliminates the need for dedicated separate circuits for each function, thereby reducing device complexity while maintaining comprehensive error checking capability.
3Reliability
If error detection and correction are performed in parallel with burst chop operations, then reliability is improved, but device complexity increases
Solution Approach 1:
The error detection circuit shares the internal data path with the burst chop operation. Both operations process the same internal data simultaneously using different control signals from the error check control circuit. This merging of data paths allows parallel error detection without requiring duplicate data storage or separate processing channels, thereby limiting the increase in device complexity.
Data Source
AI summary
A semiconductor device includes an error detection circuit configured to generate fixed data by fixing any one of a first group and a second group included in internal data to a preset level based on a burst chop signal and an internal command address in response to a read command, and generate an error detection signal by detecting an error of the fixed data; and a data output circuit configured to generate latch data by latching the internal data based on a first latch output control signal, and generate output data by serializing the latch data and the error detection signal based on a second latch output control signal.