Semiconductor System Error Detection and Correction
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Solution Overview
Problem
As semiconductor devices transmit data at faster speeds, the likelihood of errors increases, necessitating improved reliability through novel design schemes that incorporate error detection and correction mechanisms.
Innovation Solution
A semiconductor system with a medium controller and semiconductor modules that sequentially count addresses to detect row or chip errors, utilizing redundancy and spare areas to ensure error-free data transmission by switching between memory, redundancy, and spare areas based on error signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data transmission speed is increased, then operation speed is improved, but error probability increases
Solution Approach 1:
The patent applies preliminary action by performing error detection and correction operations before data transmission completes. The medium controller detects errors in received data and requests retransmission proactively, rather than waiting for errors to manifest. This allows the system to maintain high transmission speeds while ensuring data integrity through preemptive error handling.
Solution Approach 2:
The patent implements feedback mechanisms where the medium controller monitors data transmission and provides feedback about detected errors. When errors are detected, the system sends feedback signals to request retransmission of specific data packets. This closed-loop feedback system enables high-speed transmission while maintaining reliability through continuous error monitoring and correction.
2Reliability
If error detection and correction mechanisms are added, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent introduces a medium controller as an intermediary component that handles error detection and correction operations. This mediator sits between the semiconductor devices and the data transmission medium, centralizing error handling functions. By using this intermediary, the patent improves reliability without significantly increasing the complexity of individual semiconductor devices, as the error management complexity is concentrated in the dedicated controller.
Data Source
AI summary
A semiconductor system includes a medium controller and a semiconductor module. The medium controller outputs an address that is sequentially counted in a test mode, senses levels of data corresponding to the address in the test mode to determine if the data has a row error or a chip error, and changes a combination of a host address to generate and store a spare address if a combination of the address corresponds to the chip error in the test mode. The semiconductor module includes a plurality of semiconductor devices. The semiconductor module repairs the address to output the data from a redundancy area if a combination of the address corresponds to the row error. The semiconductor module outputs the data from a spare area selected by the spare address if a combination of the address corresponds to the chip error.