Semiconductor Device ESD Protection via Segmented Contact Layer
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Solution Overview
Problem
Conventional ESD protection elements using MOS transistors in semiconductor devices face inefficiencies due to the failure of parasitic bipolar transistors to turn on effectively in the finger portion near the P+ type contact layer, leading to inadequate discharge of static electricity, especially under positive static electricity surges.
Innovation Solution
A semiconductor device design featuring a P+ type contact layer surrounding the source and drain layers, with specific configurations of metal silicide layers and contact electrodes to enhance the parasitic bipolar transistor's operation, ensuring efficient discharge of static electricity by preventing hole flow into the P+ type contact layer and promoting uniform turn-on of parasitic bipolar transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the P+ type contact layer is positioned to surround the N+ type source layer, then holes are absorbed and back gate potential is stabilized, but parasitic bipolar transistors in the finger portion cannot turn on for ESD discharge
Solution Approach 1:
The patent segments the P+ type contact layer configuration into distinct spatial regions: one region surrounds the N+ type source layer to stabilize back gate potential, while another region is positioned in the finger portion away from the source layer to enable ESD discharge. This segmentation allows both functions to coexist without interfering with each other, resolving the contradiction between potential stability and transistor turn-on capability.
2Speed
If miniaturization of elements is enhanced for higher speed performance, then switching performance is improved, but electrostatic breakdown tolerance is decreased
Solution Approach 1:
The patent introduces the P+ type contact layer as an intermediary element that mediates between the miniaturized device structure and the ESD protection requirement. This intermediate structure provides a dedicated path for static electricity discharge, allowing the main device to be miniaturized for high-speed performance while the intermediary P+ layer handles the electrostatic protection function, thus resolving the contradiction between speed and tolerance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively enhances the ESD protection characteristics by ensuring immediate discharge of positive static electricity and improved thermal breakdown current, providing better protection for power LDMOS transistors against static electricity.
Implementation Method 1
holes generated by an avalanche breakdown near the N+ type drain layer
Implementation Method 2
discharge static electricity to the ground line etc through the ESD protection element
Data Source
AI summary
A semiconductor device equally turns on the parasitic bipolar transistors in the finger portions of the finger form source and drain electrodes when a surge voltage is applied, even with the P+ type contact layer surrounding the N+ type source layers and the N+ type drain layers connected to the finger form source and drain electrodes. A P+ type contact layer surrounds N+ type source layers and N+ type drain layers. Metal silicide layers are formed on the N+ type source layers, the N+ type drain layers, and a portion of the P+ type contact layer. Finger form source electrodes, finger form drain electrodes, and a P+ type contact electrode surrounding these finger form electrodes are formed, being connected to the metal silicide layers respectively through contact holes formed in an interlayer insulation film deposited on the metal silicide layers.