Semiconductor Device ESD Protection via Doped Islands
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Solution Overview
Problem
Semiconductor devices are vulnerable to electrostatic discharge (ESD) due to high trigger voltages, which can lead to damage or destruction of integrated circuits, and existing ESD protection devices require lower trigger voltages to provide immediate protection.
Innovation Solution
The semiconductor device incorporates a substrate with a gate, drain, and source regions, along with first and second well regions and doped islands of complementary conductivity types, where the doped islands are spaced apart to increase substrate resistance (Rsub), thereby reducing the trigger voltage and enabling quicker ESD protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the substrate resistance (Rsub) is kept low, then the device operation is stable, but the trigger voltage becomes higher which delays ESD protection activation
Solution Approach 1:
The substrate resistance is segmented into multiple regions with different resistance values. The first doped islands create high-resistance regions spaced apart in the source region, while maintaining low overall substrate resistance through controlled doping. This segmentation allows the device to achieve both stable operation and quick ESD protection activation by creating localized high-resistance paths that reduce trigger voltage without compromising overall device stability.
2Speed
If the trigger voltage is reduced for faster protection, then ESD protection activates quicker, but the device may become more sensitive to normal operating voltages
Solution Approach 1:
The device employs local quality by creating specific high-resistance regions through first doped islands only in the source region, while maintaining normal substrate resistance elsewhere. The first doped islands are spaced apart at specific distances to create localized resistance enhancement that reduces trigger voltage without affecting the overall device characteristics or sensitivity to normal operating voltages.
3Volume of moving object
If first doped islands are placed close to the first well region, then the structure is compact, but the substrate resistance increase is insufficient to reduce trigger voltage
Solution Approach 1:
The device uses asymmetric positioning of first doped islands relative to the first well region. The first doped islands are spaced apart at optimized distances that are not symmetrically distributed, creating asymmetric resistance patterns that maximize the substrate resistance increase. This asymmetric arrangement ensures sufficient trigger voltage reduction while maintaining compact device dimensions.
Data Source
AI summary
A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed in the substrate at two respectively sides of the gate, a first well region formed in the substrate, and a plurality of first doped islands formed in the source region. The drain region and the source region include a first conductivity, and the first well region and the first doped islands include a second conductivity. The source region is formed in the first well region, and the first doped islands are spaced apart from the first well region.