Semiconductor Device ESD Protection via Dummy Gate Ballast
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Solution Overview
Problem
Existing semiconductor technologies face challenges in providing effective electrostatic discharge (ESD) protection for modern FET devices like FinFETs and GAA NWFETs, as traditional silicide blocking methods are incompatible with these designs.
Innovation Solution
A method and structure involving dummy gate patterns with gate cut regions and a metal interconnect structure are used to create a drain-side ballast region, allowing for ESD protection by altering doping patterns and providing a circuitous current path, which is compatible with the fabrication methods of FinFETs and GAA NWFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicide blocking is used to implement drain ballast resistors, then ESD protection is improved, but compatibility with FinFET and GAA NWFET fabrication processes deteriorates
Solution Approach 1:
The invention changes the implementation approach from silicide blocking to doping-based ballast resistance. By modifying the doping parameters (using different dopant types and concentrations in dummy gate regions versus active regions), the patent achieves drain ballast functionality that is compatible with modern FinFET and GAA NWFET fabrication processes while maintaining ESD protection capabilities
Solution Approach 2:
The patent uses dummy gate patterns that replicate the structure and doping characteristics of active gate patterns. These dummy gates are positioned in the drain ballast region and receive the same doping treatment, creating regions with high resistance that provide ESD protection without requiring silicide blocking processes
2Reliability
If dummy gate patterns with gate cut regions are used to create drain ballast region, then ESD robustness is improved, but device complexity increases
Solution Approach 1:
The gate pattern is segmented into active gate regions and dummy gate regions with gate cut regions. The dummy gate patterns are divided into multiple segments (first dummy gate pattern, second dummy gate pattern) with alternating gate cut regions, creating a structured approach to forming high-resistance ballast regions while maintaining manageable fabrication complexity
Solution Approach 2:
Different regions of the gate pattern are assigned different functions: active gate regions for transistor control and dummy gate regions with gate cuts for creating high-resistance ballast regions. This local differentiation allows the device to achieve ESD protection through spatially varying doping and resistance characteristics without requiring complex overall device architecture
3Manufacturing precision
If doping is performed using dummy gate patterns as mask, then ballast region doping precision is improved, but manufacturing process steps increase
Solution Approach 1:
The dummy gate patterns are formed in advance before the doping process, serving as pre-positioned masks that define the ballast region boundaries. This preliminary structuring allows subsequent doping steps to precisely target the intended regions without requiring additional alignment steps or complex masking procedures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances ESD robustness by creating high-resistance portions under dummy gates and a low-resistance path, effectively elongating the current path between the drain and the active gate, thereby improving the driving capability and reliability of the semiconductor device.
Implementation Method 1
doping the active semiconductor patterns in the drain-side region with a second type of dopant while using the first and second dummy gate patterns as a mask to counteract doping of the active semiconductor patterns with the second type of dopant in the dummy gate regions
Implementation Method 2
forming a metal interconnect structure connecting each of the active semiconductor patterns of the second subset to at least one of the active semiconductor patterns of the first subset in a region between the first and the second dummy gate patterns
Data Source
AI summary
A semiconductor device and a method for forming such are provided, the device including: a substrate, a plurality of parallel active semiconductor patterns that extend through a drain-side region and a source-side region, a metal drain contact in the drain-side region, an active gate pattern, a first dummy gate pattern, and a second dummy gate pattern that all extend across the active semiconductor patterns, and a metal interconnect structure located in a region between the first and the second dummy gate patterns. The active semiconductor patterns are doped with a dopant in portions exposed by the dummy gates in dummy gate regions that include the gate cut regions of the first and second dummy gate patterns. The metal interconnect structure connects each of a second subset of the active semiconductor patterns to a respective at least one of a first subset of the active semiconductor patterns.