Semiconductor ESD Protection Structure for High-Voltage ICs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated circuits lack effective protection against electrostatic discharges, particularly at power supply voltages higher than several volts, and require a compact design to minimize bulk.
Innovation Solution
A semiconductor device with doped wells and regions of varying conductivity types, coupled with insulating trenches and lightly-doped regions, forms a protective structure that enhances electrostatic discharge resistance while maintaining a compact footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional protection devices are used, then electrostatic discharge protection is provided, but the device occupies significant bulk and is not compatible with high power supply voltages
Solution Approach 1:
The patent implements nesting by placing the third lightly-doped region directly beneath the insulating trench that separates the first and second doped regions. This nested configuration allows the ESD protection structure to be integrated within a compact vertical footprint, achieving high voltage protection without proportionally increasing device area. The nested arrangement of doped regions and insulating trenches creates a space-efficient protective structure.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional vertical structure by extending doped regions deep into the substrate and stacking insulating trenches and lightly-doped regions in vertical layers. This vertical dimensionality allows the device to achieve high breakdown voltages through increased vertical distance between conductive regions, while maintaining a compact lateral footprint suitable for integrated circuits.
2Adaptability or versatility
If the device is designed for high power supply voltages, then voltage compatibility is improved, but the surface area increases
Solution Approach 1:
The patent achieves high voltage compatibility by exploiting the vertical dimension rather than expanding laterally. Multiple doped regions (first, second, and third regions) are stacked vertically with insulating trenches separating them, creating a vertical voltage distribution path. This allows the device to withstand high power supply voltages through increased vertical breakdown distance while maintaining a compact lateral footprint that does not significantly increase surface area.
Solution Approach 2:
The nested configuration of vertically stacked doped regions and insulating trenches allows the high-voltage protection structure to be embedded within a compact footprint. The third lightly-doped region is positioned beneath the insulating trench, creating a nested arrangement that maximizes voltage handling capability within minimal lateral space, thus achieving voltage compatibility without proportional surface area increase.
Data Source
AI summary
An electronic device includes a doped semiconductor substrate of a first conductivity type. First and second doped wells are provided, separated from each other by trench isolation, within the doped semiconductor substrate. At least one first region and at least one second region are respectively located in the first and second doped wells, with each first and second region having a doping level higher than a doping level of the first and second doped wells. The trench isolation penetrates into the first and second doped wells and extends laterally between the first region and second region. A third region laterally extends between the first and second doped wells at a location under the insulating trench. The third region has a doping level lower than the doping level of the first and second doped wells.