Stacked Semiconductor Device ESD Protection via Interposer Extraction
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Solution Overview
Problem
The miniaturization of MOS planar transistors and memory cells in semiconductor devices is hindered by the difficulty in integrating additional input and output terminals due to increased area requirements for electro-static discharge (ESD) protection circuits, which limits memory capacity and increases the risk of ESD failures in stacked semiconductor devices.
Innovation Solution
A method where input terminals without ESD protection circuits are kept at the same electrical voltage level using a conductive seed layer or shunt wiring before chip stacking, allowing them to be connected with output terminals post-stacking, thereby preventing ESD exposure and reducing the need for additional manufacturing steps or tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD protection circuits are added to input terminals, then reliability against electro-static discharge is improved, but area of the chip increases and manufacturing complexity increases
Solution Approach 1:
The patent extracts the ESD protection function from traditional input protection circuits and relocates it to the interposer substrate. By forming ESD protection circuits on the interposer rather than on the chip itself, the chip area is preserved while ESD protection functionality is maintained through the interposer's dedicated protection structures.
Solution Approach 2:
The interposer acts as an intermediary between the chip and the external environment. It provides ESD protection at the interface level, mediating the electro-static discharge threats before they reach the chip's input terminals. This allows the chip to maintain minimal area while the interposer handles the protection function.
2Reliability
If ESD protection circuits are added to input terminals, then reliability against electro-static discharge is improved, but device complexity increases
Solution Approach 1:
The patent merges the ESD protection circuit formation process with the existing TSV (through-silicon via) manufacturing process. By combining these functions into a single integrated approach on the interposer, the patent reduces overall manufacturing complexity compared to adding separate ESD protection steps for each chip.
Solution Approach 2:
The interposer is designed to provide ESD protection services automatically through its inherent structure and circuits. The ESD protection circuits on the interposer self-activate when ESD events occur, protecting the chip without requiring additional control mechanisms or complex manufacturing interventions.
3Productivity
If number of input and output terminals is increased, then data transfer capability is improved, but area for ESD protection circuits increases
Solution Approach 1:
The patent moves the ESD protection functionality from the two-dimensional chip surface to the interposer substrate, effectively utilizing a different spatial dimension. This allows increased terminal density on the chip while ESD protection resources are allocated on the interposer, resolving the area conflict.
Solution Approach 2:
The patent segments the ESD protection function from the chip and assigns it to the interposer. This segmentation allows the chip to focus on high-density terminal integration for data transfer, while the interposer handles the ESD protection responsibilities, enabling both high productivity and efficient area utilization.
Data Source
AI summary
A method of manufacturing a stacked semiconductor device having two or more wafers may include forming a conductor on an upper wafer, the conductor configured to electrically connect input terminals together that have no input protection circuit against ESD; forming front side micro-bumps on a front side of the upper wafer, the front side micro-bumps configured to electrically connect to back side micro-bumps on the upper wafer; forming a TSV structure, the TSV structure configured to facilitate electrical connections between the front and the back side of the upper wafer; forming back side micro-bumps on the back side of the upper wafer, the back side micro-bumps configured to electrically connect with front side micro-bumps on the lower wafer; stacking the upper wafer on the lower wafer; and separating the conductor such that each of the input terminals are electrically independent from other ones of the input terminals.