Semiconductor ESD Protection Circuit Delayed Switch Timing
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Solution Overview
Problem
Existing ESD protection circuits in semiconductor apparatuses can malfunction due to instantaneous changes in power supply voltage, particularly when the power supply is unstable, leading to potential breakdowns and failure in delivering stable power, especially in power supply ICs.
Innovation Solution
A semiconductor apparatus with a protection circuit comprising a series circuit of a resistor and capacitor connected in parallel with an NMOS transistor, and a switch circuit that turns on after the power supply voltage is applied, ensuring the NMOS transistor is kept off and preventing malfunctions caused by voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the NMOS transistor is kept OFF during power supply voltage application to prevent malfunction, then reliability is improved, but the circuit cannot respond to ESD surge voltages effectively
Solution Approach 1:
The switch circuit is configured to turn ON in a delayed manner after power supply voltage is applied, establishing a predetermined timing sequence where the switch closes after the NMOS transistor has been reliably turned OFF. This preliminary timing arrangement ensures that ESD protection is activated only when stable power supply conditions are confirmed, preventing both malfunction and ESD damage.
Solution Approach 2:
The circuit uses the power supply voltage itself as a feedback signal to control the timing of the switch circuit. The delayed turn-ON of the switch is triggered by the presence and stability of the power supply voltage, creating a feedback mechanism that automatically adjusts the ESD protection activation based on power supply conditions.
2Object-affected harmful factors
If the switch circuit turns on immediately after power supply voltage is applied, then ESD protection is activated quickly, but the NMOS transistor may turn on due to unstable power supply voltage causing malfunction
Solution Approach 1:
The circuit establishes a predetermined delay period before the switch circuit turns ON, allowing the power supply voltage to stabilize first. This preliminary waiting period ensures that the NMOS transistor remains reliably OFF during voltage fluctuations, and only after stability is confirmed does the ESD protection activate.
Solution Approach 2:
The delayed timing arrangement acts as a cushioning mechanism, protecting the NMOS transistor from the harmful effect of premature activation during unstable power supply conditions. By cushioning the activation timing, the circuit prevents malfunction while ensuring subsequent ESD protection capability.
3Reliability
If a delay period is introduced before the switch circuit turns on, then malfunction prevention is improved, but response time to ESD events is increased
Solution Approach 1:
The circuit employs periodic or phased action where the switch circuit operates in distinct stages: first remaining OFF during the delay period to prevent malfunction, then turning ON to provide ESD protection. This phased timing optimizes both reliability and response time by activating protection only when necessary.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents ESD breakdowns and malfunctions by ensuring the NMOS transistor remains off during stable power supply conditions, thereby protecting internal circuits from surge voltages and maintaining stable power delivery.
Implementation Method 1
a series circuit including a resistor and a first capacitor connected in series
Implementation Method 2
an NMOS transistor connected in parallel with the series circuit, the NMOS transistor configured to be controlled in accordance with a voltage at a connection point between the resistor and the capacitor
Data Source
AI summary
A semiconductor apparatus includes: first and second power-supply terminals; an internal circuit connected between the first and second power-supply terminals; and a protection circuit connected in parallel with the internal circuit between the first and second power-supply terminals, the protection circuit including: a series circuit that includes a resistor and a first capacitor, and is connected in parallel with the internal circuit between the first and second power-supply terminals; a first MOS transistor that is connected in parallel with the series circuit, and is controlled according to a voltage at a connection point between the resistor and the first capacitor; and a switch circuit that is connected in parallel with the resistor, is turned on in a delayed manner after a power-supply voltage is applied between the first and second power-supply terminals, and changes the voltage at the connection point so that the first MOS transistor is turned off.