Semiconductor ESD Protection Circuit Topology
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Solution Overview
Problem
Semiconductor devices face ESD breakdown due to successive pulses, as existing ESD protective elements fail to fully discharge electric charges stored in internal circuits, leading to progressive accumulation and eventual destruction of internal circuit gates.
Innovation Solution
Incorporating a second electrostatic protective element between power supply interconnects and ground electrode, which provides an additional current path when the potential reaches a specific threshold, enhancing the discharge of electric charges and reducing the resistance for effective ESD protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single ESD protective element is disposed near the pad, then the device structure is simple, but electric charges accumulate in internal circuits during successive ESD pulses
Solution Approach 1:
The ESD protection function is segmented into two distinct protective elements: a first ESD protective element connected between the pad and internal circuit, and a second ESD protective element connected between the power supply interconnect and ground. This segmentation allows each element to handle different aspects of ESD protection, preventing charge accumulation in internal circuits during successive pulses.
Solution Approach 2:
The power supply interconnect serves as an intermediary node that enables the second ESD protective element to provide an alternative discharge path. By introducing this intermediary connection, charges can be discharged through the power supply network rather than accumulating in the internal circuit gates.
2Object-affected harmful factors
If ESD protective elements are disposed near pads, then protection against ESD surges is provided, but charges are not fully discharged during successive pulses
Solution Approach 1:
The protection scheme adds a dimensional aspect by utilizing the power supply network as an additional discharge dimension. Instead of relying solely on the direct pad-to-ground path, charges can now be discharged through the power supply interconnect dimension, providing more complete energy dissipation during successive ESD pulses.
3Reliability
If multiple discharge paths are provided, then ESD protection effectiveness increases, but device complexity increases
Solution Approach 1:
The second ESD protective element utilizes the existing power supply interconnect structure for its operation. By making the power supply network serve a dual function (power delivery and ESD charge discharge), the patent achieves enhanced protection without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents ESD breakdown by providing multiple discharge paths, ensuring efficient discharge of electric charges and increasing the semiconductor device's withstand voltage against ESDs, even under successive pulse applications.
Implementation Method 1
a first electrostatic protective element providing a current path from the first interconnect to the second interconnect when the potential on the first interconnect reaches a first threshold value
Implementation Method 2
a second electrostatic protective element disposed between the power supply interconnect and the second interconnect, the second electrostatic protective element providing a current path from the power supply interconnect to the second interconnect when the potential on the first interconnect reaches a second threshold value
Data Source
AI summary
A semiconductor device is disclosed, which includes first and second power supply pads supplied with first and second power voltages, respectively, a first protection circuit coupled between the first and second power supply pads, and an internal circuit including a first power line and a plurality of transistors electrically coupled to the first power line. The first power line includes first and second portions, and the first portion is electrically connected to the first power supply pad. The device further includes a second protection circuit coupled between the second portion of the first power line and the second power supply pad.


