Semiconductor ESD Layout With Multiple SCR Discharge Paths

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Solution Overview

Problem

Existing semiconductor devices face challenges with voltage overshoot during electrostatic discharge (ESD) events, particularly with diode string triggered SCRs (DTSCRs) and low voltage triggered SCRs (LVTSCRs, which require improved performance due to capacitance factors.

Innovation Solution

The semiconductor device incorporates a configuration with diodes Dp, Dn, and Dn′, along with a power clamp circuit and resistance, forming multiple ESD paths and equivalent silicon controlled rectifier (SCR) circuits to effectively discharge ESD current and reduce voltage drop across internal circuits, enhancing ESD robustness and reducing parasitic capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If DTSCR is used for ESD protection, then ESD robustness is improved, but voltage overshoot occurs during ESD events

Engineering Contradiction:

ImproveESD robustnessVSAvoidvoltage overshoot

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent divides the ESD protection function into multiple independent paths: a first ESD path through a first SCR and a second ESD path through a second SCR. Each SCR handles a portion of the ESD current, preventing voltage overshoot while maintaining ESD robustness through distributed current management

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If LVTSCR is used for ESD protection, then capacitance is reduced, but ESD performance requires improvement

Engineering Contradiction:

ImprovecapacitanceVSAvoidESD performance

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent merges multiple SCR structures into a unified ESD protection system where first and second SCRs operate together. This combination achieves low capacitance through the LVTSCR architecture while improving ESD performance through the coordinated operation of multiple protection paths

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent employs dynamic triggering mechanisms where the first SCR can be triggered by a first trigger signal and the second SCR by a second trigger signal. This dynamic control allows optimization of ESD response characteristics while maintaining low capacitance through selective activation of protection paths

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS11929363B2Semiconductor device having multiple electrostatic discharge (ESD) paths

Publication Date: 2024.03.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

In some embodiments, a semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.