Semiconductor ESD Protection via Sub-surface Current Steering
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Solution Overview
Problem
Semiconductor devices face damage from electrostatic discharge (ESD) due to high power density, and existing ESD protection methods are inadequate in providing efficient discharge paths, especially in power-saving ICs with reduced feature sizes and increased circuit density.
Innovation Solution
The semiconductor device incorporates a gate structure with doped contact regions of opposing conductivity types, including a well doped region and third doped contact regions surrounded by these, which enhance ESD protection by forcing ESD current to flow sub-surficially and utilizing parasitic bipolar junction transistors to improve efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the feature size is reduced to increase circuit density, then the circuit density and efficiency are improved, but the ESD protection capability deteriorates due to reduced discharge path capacity
Solution Approach 1:
The patent transitions the ESD discharge path from a planar surface configuration to a three-dimensional sub-surface configuration. The doped contact regions extend vertically into the semiconductor substrate, creating depth-based discharge paths that bypass the limitations of surface area scaling. This dimensional transition allows ESD protection to maintain effectiveness even as lateral feature sizes are reduced for higher circuit density.
Solution Approach 2:
The patent embeds multiple doped contact regions of alternating conductivity types within the semiconductor substrate, creating nested protective structures. The third doped contact regions (opposite conductivity type) are surrounded by first and second doped contact regions, forming concentric protective zones that guide ESD current through multiple confined paths within the substrate volume.
2Reliability
If a separate ESD protection device is added, then the ESD protection efficiency is improved, but the device area increases
Solution Approach 1:
The patent integrates ESD protection functionality directly into the existing semiconductor device structure by incorporating doped contact regions into the substrate alongside normal circuit elements. The gate structures serve dual purposes: as switching elements for normal operation and as components of the ESD discharge path when activated, eliminating the need for separate dedicated ESD protection devices and reducing overall device area.
Solution Approach 2:
The doped contact regions and gate structures are designed to perform multiple functions: they serve as normal circuit components during standard operation and automatically activate as ESD protection elements during electrostatic discharge events. This multi-functionality allows a single structure to provide both circuit operation and ESD protection, reducing the need for additional dedicated protection components.
3Strength
If the dopant concentration of drain region is decreased to increase breakdown voltage, then the breakdown voltage is improved, but the ESD discharge capability deteriorates due to reduced current handling capacity
Solution Approach 1:
The patent applies different dopant concentrations to different regions of the semiconductor substrate. The drain region maintains lower dopant concentration for high breakdown voltage, while the doped contact regions (first, second, and third) have higher dopant concentrations specifically optimized for ESD current handling. This localized differentiation allows each region to be optimized for its specific function without compromising the other.
Solution Approach 2:
The patent divides the ESD discharge path into multiple segmented doped contact regions distributed throughout the substrate. Rather than relying on a single high-current path, the ESD current is distributed across multiple first, second, and third doped contact regions, each contributing to the overall discharge capability. This segmentation allows the system to achieve high ESD capability without requiring any single region to have excessively high current density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly improves ESD protection efficiency, as demonstrated by a 2.2 times increase in transmission line pulse current while maintaining similar trigger and holding voltages, and allows for reduced device area by integrating ESD protection within the same device as an output driver.
Implementation Method 1
utilizing parasitic bipolar junction transistors to improve efficiency
Data Source
AI summary
A semiconductor device and a manufacturing method for the same are provided. The semiconductor substrate includes a gate structure, a first doped contact region, a second doped contact region and a well doped region. The gate structure is on the semiconductor substrate, and has a first gate sidewall and a second gate sidewall opposite to the first gate sidewall. The first doped contact region has a first type conductivity and is formed in the semiconductor substrate on the first gate sidewall of the gate structure. The second doped contact region has the first type conductivity and is formed in the semiconductor substrate on the second gate sidewall of the gate structure. The well doped region has the first type conductivity and is under the first doped contact region.