Semiconductor Integrated Circuit ESD Tolerance Optimization
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges in achieving high Electrostatic Discharge (ESD) tolerance without increasing chip area, particularly in the design of power conversion bridge circuits where the high-voltage junction termination structure (HVJT) and level shifter configurations lead to parasitic operations and local current concentration.
Innovation Solution
The semiconductor integrated circuit design incorporates a high-potential-side circuit region with a looped drift region and a buried layer, along with a carrier supply and reception region, to improve ESD tolerance by optimizing the distance and impurity concentration between these regions, thereby reducing the electric field concentration and preventing parasitic operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the HVJT and level shifter are designed with uniform drift region length to achieve uniform off-state breakdown voltage, then avalanche current flows uniformly through both structures, but this causes parasitic n-p-n bipolar transistor turn-on in the level shifter and induces parasitic operation leading to easy damage
Solution Approach 1:
The patent applies local quality by making the drift region length of the level shifter different from that of the HVJT. Specifically, the level shifter's drift region is designed to be longer than the HVJT's drift region, creating non-uniform characteristics in different parts of the circuit. This local differentiation causes the level shifter to have higher breakdown voltage than the HVJT, ensuring that during ESD events, the HVJT breaks down first and dissipates the surge current before it can trigger parasitic transistors in the level shifter, thus eliminating the parasitic operation problem while maintaining ESD tolerance.
2Reliability
If the level shifter drift region is made longer than the HVJT drift region to improve ESD breakdown tolerance, then ESD tolerance increases, but the effective area of the high-side circuit decreases
Solution Approach 1:
The patent resolves the area constraint by changing the spatial arrangement from a linear extension approach to a vertical stacking approach. Instead of extending the drift region horizontally which would consume more chip area, the level shifter is positioned vertically above the HVJT structure. This three-dimensional arrangement allows the level shifter to have a longer drift region length (improving ESD tolerance) while occupying minimal additional planar area, thus preserving the effective area of the high-side circuit.
3Reliability
If the level shifter drift region protrudes toward the outer circumferential side of the ground region, then ESD tolerance is improved, but the chip area increases
Solution Approach 1:
The patent applies the nesting principle by placing the level shifter structure within or adjacent to the existing HVJT structure. The level shifter's drift region is configured to extend vertically rather than horizontally outward, effectively nesting the level shifter within the boundary defined by the HVJT and ground region. This nested arrangement allows the level shifter to achieve its required drift region length for improved ESD tolerance without protruding beyond the existing circuit boundaries, thereby avoiding any increase in chip area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances ESD tolerance without expanding the chip area, allowing for more flexible design possibilities and improved reliability by managing avalanche currents effectively.
Implementation Method 1
When an electrostatic discharge (ESD) surge, for example, is input to the power supply terminal on the high-potential side, the HVJT and the level shifter are simultaneously led to an avalanche phenomenon
Implementation Method 2
a carrier supply region of a first conductivity type provided in the looped well region, and included in a level conversion element included in a level shift circuit
Data Source
AI summary
A semiconductor integrated circuit includes a high-potential-side circuit region, a high-voltage junction termination structure surrounding the high-potential-side circuit region, and a low-potential-side circuit region surrounding the high-potential-side circuit region via the high-voltage junction termination structure which are integrated into a single chip, and wherein a first distance between a looped well region and a buried layer in a region in which a first contact region is formed is smaller than a second distance between the looped well region and the buried layer in a region in which a carrier reception region is formed.