Semiconductor Device Etch Barrier Pattern for Gate Isolation
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Solution Overview
Problem
Existing semiconductor devices face challenges in preventing the unintentional connection between dummy gate electrodes and source/drain regions during fabrication, leading to reliability issues due to the complexity of forming uniform gate insulating layers on etched epitaxial layers.
Innovation Solution
The formation of an etch barrier pattern on the field insulating layer, comprising insulating patterns like silicon oxide and silicon nitride layers, prevents the epitaxial layers from being connected to the dummy gate by extending between the source/drain regions and the gate, ensuring proper separation and reliable device construction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate insulating layers are formed on etched epitaxial layers, then the gate electrode can be properly positioned, but unintentional connection between dummy gate electrodes and source/drain regions occurs
Solution Approach 1:
The patent extracts and removes the problematic etched epitaxial layer material from between the source/drain regions and the dummy gate electrode using a selective removal process. This eliminates the source of unintentional connection while preserving the necessary gate insulating layer formation on the fin region, thereby resolving the contradiction between manufacturing precision and device reliability.
Solution Approach 2:
The patent applies preliminary anti-action by performing a selective removal process before the final gate electrode formation. This preliminary action prevents the potential harm of unintentional connections by removing the etched epitaxial layer material that would otherwise create conductive paths between the source/drain regions and the dummy gate electrode.
2Adaptability or versatility
If dummy gate electrodes are formed extending over source/drain regions, then multi-gate transistor structure is achieved, but unwanted connections occur between dummy gate and source/drain regions
Solution Approach 1:
The patent extracts and removes the conductive etched epitaxial layer material from the region between the source/drain regions and the dummy gate electrode. This selective removal maintains the multi-gate transistor structure with the dummy gate electrode extending over the source/drain regions while eliminating the unwanted conductive connections, thereby resolving the contradiction between structural adaptability and device reliability.
3Manufacturing precision
If complex fabrication processes are used to form uniform gate insulating layers, then proper gate positioning is achieved, but device reliability decreases due to unintentional connections
Solution Approach 1:
The patent simplifies the fabrication process by extracting and removing the problematic etched epitaxial layer material in a selective removal step. This approach maintains the ability to form uniform gate insulating layers on the fin region while eliminating the source of unintentional connections, thereby reducing fabrication process complexity without compromising manufacturing precision.
Solution Approach 2:
The patent performs a preliminary selective removal action to eliminate the etched epitaxial layer material before subsequent gate electrode formation steps. This preliminary action prevents future reliability issues without requiring complex modifications to the gate insulating layer formation process, thereby reducing overall fabrication complexity while maintaining manufacturing precision.
Data Source
AI summary
A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.