Semiconductor Etch Mask Patterning Beyond Lithography Limits

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Solution Overview

Problem

The feature size of exposure lines in semiconductor manufacturing approaches the theoretical resolution limit, leading to distorted imaging of silicon wafers and a deterioration in photolithographic pattern quality.

Innovation Solution

A method involving the formation of patterned sacrificial layers, where a first sacrificial layer is patterned on a surface, a second sacrificial layer is formed in an opening, and a third sacrificial layer is generated through a reaction between the first and second layers, allowing for the creation of a patterned mask structure for etching the semiconductor device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the minimum linewidth and spacing are continuously reduced to increase capacity per unit area, then the capacity per unit area is increased, but the feature size approaches the theoretical resolution limit causing distorted imaging and deterioration in photolithographic pattern quality

Engineering Contradiction:
Improvecapacity per unit areaVSAvoidphotolithographic pattern quality
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent divides the patterning process into multiple stages using different sacrificial layers (first, second, and third sacrificial layers) with different functions. The first sacrificial layer defines opening positions, the second sacrificial layer forms the actual pattern, and the third sacrificial layer protects specific areas. This segmentation allows each layer to be optimized for its specific function, enabling precise pattern formation without being constrained by the resolution limits of a single lithographic step.

Inventive Principle:
Principle #1Segmentation

2Length of moving object

If the feature size of exposure lines is reduced to achieve smaller device dimensions, then device dimensions are reduced, but imaging distortion increases and pattern quality deteriorates

Engineering Contradiction:
Improvedevice dimensionsVSAvoidpattern quality
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The patent transitions from two-dimensional planar patterning to three-dimensional multi-layer sacrificial layer structures. By stacking multiple sacrificial layers vertically and using their different heights and positions, the invention achieves precise lateral pattern definition without requiring extremely small feature sizes in the lithographic exposure step. The vertical dimension provides an additional degree of freedom for pattern control.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The sacrificial layers serve as intermediary structures that mediate between the lithographically defined patterns and the final etched patterns. The first sacrificial layer acts as an intermediary to define opening positions, while the second sacrificial layer fills these openings to create the actual pattern. This intermediary approach allows the final pattern dimensions to be determined by the sacrificial layer geometry rather than directly by the lithographic resolution limit.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables larger feature sizes in sacrificial layers, facilitating further reduction in device dimensions, improving yield, increasing production efficiency, and reducing costs.

Implementation Method 1

forming a third sacrificial layer via a reaction between the first sacrificial layer and the second sacrificial layer at the contact face

Methodology Applied
Scientific EffectChemical reaction: Chemical Bonding

Data Source

PatentUS11848188B2Semiconductor device and method for manufacturing the same
Publication Date: 2023.12.19 CHANGXIN MEMORY TECH INC
  • US11848188B2 patent drawing
  • US11848188B2 patent drawing
  • US11848188B2 patent drawing

AI summary

A method for manufacturing the semiconductor device includes: providing a layer to be etched; on a surface of the layer to be etched, forming a first sacrificial layer that is patterned and includes an opening for exposing the layer to be etched; forming a second sacrificial layer in the opening, the second sacrificial layer having a contact face contacted with the first sacrificial layer; forming a third sacrificial layer via a reaction between the first sacrificial layer and the second sacrificial layer at the contact face; removing at least one of at least part of an unreacted portion of the first sacrificial layer and the second sacrificial layer to form a patterned mask structure; etching the layer to be etched based on the patterned mask structure to form an etched pattern.