Etch Stop Structure for Semiconductor Memory Peripheral Protection
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Solution Overview
Problem
Existing semiconductor fabrication methods require complex and costly photolithographically-patterned masks to form etch stops over peripheral regions without damaging memory arrays, introducing risks of misalignment and increased complexity.
Innovation Solution
A method of patterning an etch stop over a peripheral region without using a photolithographically-patterned mask, involving the formation of electrically insulative materials with different compositions to create a structure with an upwardly-extending stem and horizontally-extending bench, allowing for selective removal and self-aligned interconnect formation between memory and peripheral regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a photolithographically-patterned mask is used to form an etch stop over the periphery, then the peripheral circuitry is protected during material removal, but the fabrication process complexity and cost increase
Solution Approach 1:
The method forms a conformal insulative layer over the entire structure before any etching occurs. This preliminary formation of the insulative layer serves as a built-in protective measure for the periphery, eliminating the need for separate mask patterning steps to protect peripheral circuitry during subsequent material removal operations.
Solution Approach 2:
The conformal insulative layer automatically provides etch stop protection where needed (over the periphery) without requiring external masking. The layer's conformal nature causes it to self-align with the underlying structure, providing automatic protection exactly where the periphery exists without additional patterning steps.
2Manufacturing precision
If a photolithographically-patterned mask is used to form an etch stop over the periphery, then selective protection is achieved, but mask misalignment risks are introduced
Solution Approach 1:
The conformal insulative layer forms automatically over the existing structure, using the structure itself as the template. This self-aligned approach eliminates mask misalignment risks entirely, as the protective layer precisely follows the contours of the underlying periphery without requiring separate patterning alignment steps.
Solution Approach 2:
By forming the insulative layer conformally before any etching operations, the method ensures that the protective layer is already in its final, precisely-aligned position. This preliminary conformal formation eliminates the need for subsequent alignment-critical patterning steps that would introduce misalignment risks.
3Productivity
If material is removed from between tightly-spaced components of a memory array, then interconnect formation is enabled, but peripheral circuitry may be damaged without protection
Solution Approach 1:
The conformal insulative layer acts as an intermediary protective barrier between the etching process and the peripheral circuitry. During material removal from the memory array regions, this layer remains intact over the periphery, serving as a mediator that allows aggressive etching in the array regions while protecting the sensitive peripheral circuitry from damage.
Solution Approach 2:
The insulative layer is formed in advance before any material removal occurs. This preliminary protective layer is already in place when etching begins, enabling immediate and aggressive material removal from the memory array regions without risk of peripheral damage, thus maximizing interconnect formation efficiency while ensuring peripheral protection.
Data Source
AI summary
Some embodiments include methods in which first insulative material is formed across a memory region and a peripheral region of a substrate. An etch stop structure is formed to have a higher portion over the memory region than over the peripheral region. A second insulative material is formed to protect the lower portion of the etch stop structure, and the higher portion is removed. Subsequently, at least some of the first and second insulative materials are removed. Some embodiments include semiconductor constructions having a first region with first features, and a second region with second features. The first features are closer spaced than the second features. A first insulative material is over the second region and an insulative structure is over the first insulative material. The structure has a stem joined to a bench. The bench has an upper surface, and the stem extends to above the upper surface.