Semiconductor Etching Pattern Level Control via Spacer Formation
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Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in achieving precise control over etching patterns, particularly in creating distinct top surface levels between cell and peripheral etching patterns, which affects the three-dimensional etching process and subsequent spacer formation, leading to inefficiencies and complexities in the fabrication process.
Innovation Solution
The method involves forming a first and second etching pattern structure on a substrate, followed by the creation of spacer layers, where a three-dimensional etching effect is utilized to differentiate the top surface levels of the cell and peripheral etching patterns, allowing for the formation of spacers that expose the lateral surfaces and enabling a simplified fabrication process by eliminating the need for additional mask patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional planar etching patterns are used, then the fabrication process is simpler, but the control over etching pattern precision and three-dimensional structure formation is insufficient
Solution Approach 1:
The patent transitions from traditional planar (2D) etching patterns to three-dimensional etching pattern structures with different top surface levels. By forming cell etching patterns and peripheral etching patterns at different heights, the invention enables precise control over etching processes while maintaining fabrication feasibility through sequential layer formation and selective etching.
Solution Approach 2:
The etching patterns are segmented into distinct cell etching patterns and peripheral etching patterns with different top surface levels. This segmentation allows independent control and optimization of etching parameters for different regions, achieving precise manufacturing control while organizing the complexity into manageable segments.
2Manufacturing precision
If additional mask patterns are used to create different top surface levels, then the etching pattern control is improved, but the fabrication process becomes more complex and time-consuming
Solution Approach 1:
The different top surface levels are created through preliminary formation of etching patterns at different heights before the main etching process. By pre-establishing the three-dimensional structure with cell etching patterns and peripheral etching patterns at different levels, the invention eliminates the need for additional mask patterns and intermediate steps, reducing fabrication time while maintaining precision.
Solution Approach 2:
The invention extracts and eliminates the need for additional mask patterns by directly forming etching patterns at different top surface levels during the initial patterning process. This extraction of unnecessary intermediate steps simplifies the fabrication process and reduces overall manufacturing time.
3Productivity
If the first spacer layer is not fully exposed during etching, then the lateral surface protection is maintained, but the spacer formation precision and subsequent process efficiency are reduced
Solution Approach 1:
The etching process utilizes plasma (a state of matter similar to gas) to selectively remove material. By controlling the plasma etching conditions, the invention achieves precise exposure of the first spacer layer during etching, enabling accurate spacer formation while maintaining high fabrication efficiency through selective material removal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the difference in level between cell and peripheral etching patterns, simplifies the fabrication process, and ensures the preservation of peripheral etching patterns for subsequent processes, thereby improving the overall efficiency and precision of semiconductor device manufacturing.
Implementation Method 1
a three-dimensional etching effect is utilized to differentiate the top surface levels of the cell and peripheral etching patterns
Data Source
AI summary
A method of fabricating a semiconductor device includes forming a first etching pattern structure and a second etching pattern structure on a substrate. The first cell etching pattern structure has a top surface at a level that is different from that of a top surface of the second etching pattern structure. The method further includes forming a first spacer layer on the first etching pattern structure and the second etching pattern structure. The first spacer layer covers top and lateral surfaces of the first etching pattern structure and top and lateral surfaces of the second etching pattern structure. The method further includes performing a first etching process on the first spacer layer to form a first spacer and a second spacer. The first spacer layer is fully exposed during the first etching process of the first spacer layer.