Semiconductor Etching Residue Removal via Segmented Lithography
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Solution Overview
Problem
Conventional lithography processes in semiconductor fabrication face challenges such as target layer residues and exposure of patterned layers, leading to decreased yield in device production, particularly during the double patterning technique (DPT) processes like LELE, which affect the quality and reliability of semiconductor devices.
Innovation Solution
A method involving sequential formation of target layers and masks on a substrate, followed by specific etching processes to form characteristic structures, eliminate residues, and fully remove the target layer, ensuring no residues remain between structures and preventing patterned layer exposure, thereby enhancing device yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a double patterning technique (LELE approach) is used to increase half-pitch resolution, then the resolution is improved, but target layer residues remain on the substrate between stripe patterned target layers
Solution Approach 1:
The patent segments the etching process into three distinct stages: first etching to form initial stripe patterns, second etching to remove target layer in spaces between stripes, and third etching to remove remaining target layer residues. This segmentation allows each etching step to have a specific function, ensuring complete removal of target layer material while maintaining the high-resolution stripe patterns.
Solution Approach 2:
The patent applies preliminary action by performing the first etching process to create stripe patterned target layers before subsequent etching steps. The etch mask is strategically positioned and patterned in advance to define the exact regions where target layer should be removed, preventing residues from forming in the first place.
2Manufacturing precision
If a double patterning technique (LELE approach) is used to increase half-pitch resolution, then the resolution is improved, but the stripe patterned target layer may be exposed from the overlying etch mask due to trimming effect
Solution Approach 1:
The patent applies local quality by using different etching conditions and mask configurations for different regions of the substrate. The etch mask is designed with specific thickness and material properties in different areas to control the etching depth locally, preventing over-etching that would expose the stripe patterned target layer while ensuring complete removal of target layer in other regions.
3Device complexity
If conventional lithography process is used, then the process is simple, but it meets limitations due to printability and manufacturability problems at small dimensions
Solution Approach 1:
The patent segments the single lithography step into multiple sequential lithography and etching steps. The first lithography process creates initial patterns, followed by etching, then a second lithography process refines the patterns further. This segmentation allows each step to work within the capabilities of conventional lithography tools while achieving overall higher resolution than a single step could provide.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively eliminates target layer residues and exposed patterned layers, improving the yield and quality of semiconductor devices by preventing epitaxial growth defects and maintaining pattern integrity during subsequent processes.
Implementation Method 1
a first etching process is performed to etch away a portion of the first mask and a portion of the target layer using the first patterned mask as an etching mask
Data Source
AI summary
The present invention provides a method for fabricating a patterned structure in a semiconductor device, which includes the following processes. First, a target layer, a first mask and a first patterned mask are sequentially formed on a substrate. Then, a first etching process is performed to form a plurality of characteristic structures on the substrate, wherein each of the characteristic structures comprises a patterned first mask and a patterned target layer. A second patterned mask is formed on the substrate, wherein the second patterned mask covers a portion of the characteristic structures and exposes a predetermined region. A second etching process is performed to fully eliminate the characteristic structures within the predetermined region. Finally, a third etching process is performed to fully eliminate the target layer not covered by the patterned first mask.