Semiconductor Etching Temperature Gradient Control
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Solution Overview
Problem
As semiconductor processes advance and component sizes shrink, existing salicide processes struggle to maintain metal silicide quality and contact hole integrity, particularly in reducing critical dimensions and improving vertical sidewall profiles.
Innovation Solution
A semiconductor process that increases the temperature gradient by positioning a wafer on a pedestal and lifting it closer to a heating source, creating a temperature difference greater than 180°C between the showerhead and pedestal, thereby controlling etching rates and enhancing cleaning efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the temperature gradient between showerhead and pedestal is increased, then lateral etching rate is reduced and bottom cleaning efficiency is improved, but vertical etching rate may be affected
Solution Approach 1:
The patent applies parameter changes by precisely controlling the temperature gradient between the showerhead and pedestal, maintaining a temperature difference of 180-220°C. This specific parameter range optimizes the balance between reducing lateral etching (improving profile precision) and maintaining vertical etching rate (ensuring productivity). The temperature parameters are carefully selected to achieve the desired contact hole geometry without sacrificing etching speed.
2Quantity of substance
If component size is reduced, then semiconductor density increases, but metal silicide quality and contact hole integrity deteriorate
Solution Approach 1:
The patent applies local quality by creating a non-uniform temperature distribution across the wafer surface through the temperature gradient between showerhead and pedestal. Different regions of the contact hole experience different temperatures: the bottom receives higher temperature for effective cleaning, while the sidewalls experience controlled temperature to minimize lateral etching. This localized temperature control enables precise manipulation of etching behavior at different locations, maintaining quality despite smaller component dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process reduces lateral etching rates, improves bottom cleaning efficiency, and maintains vertical etching rates, resulting in smaller critical dimensions and vertical sidewall profiles for contact holes, enhancing metal silicide quality and semiconductor component reliability.
Implementation Method 1
an annealing process is performed on the wafer by the heating source
Implementation Method 2
increasing the temperature gradient of the wafer, such as increasing the temperature difference between a showerhead and a pedestal at both sides of the wafer
Implementation Method 3
the temperature surrounding the wafer during the etching process can be higher than the temperature without the pedestal being approached. Therefore, the etching rate to the wafer can be decreased thanks to the higher temperature
Data Source
AI summary
A semiconductor process includes the following steps. A wafer on a pedestal is provided. The pedestal is lifted to approach a heating source and an etching process is performed on the wafer. An annealing process is performed on the wafer by the heating source. In another way, a wafer on a pedestal, and a heating source on a same side of the wafer as the pedestal are provided. An etching process is performed on the wafer by setting the temperature difference between the heating source and the pedestal larger than 180° C.