Semiconductor Evaluation Apparatus Insulation Design
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Solution Overview
Problem
Conventional semiconductor evaluation apparatuses face challenges in securing insulation due to large high-voltage areas and close proximity of chuck stages and probe contact regions, leading to accuracy deterioration and insulation difficulties as voltage increases.
Innovation Solution
A semiconductor evaluation apparatus with a movable semiconductor wafer holding portion, front surface probe, back surface connecting portion, and back surface potential lead-out portion, which reduces the high-potential area by moving these components in the in-plane direction, allowing for shorter wiring and reduced parasitic inductance, thereby enhancing insulation and evaluation accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a long cable is used to connect the chuck stage to the evaluation unit, then the chuck stage can be positioned away from the measurement area, but the parasitic inductance increases and evaluation accuracy deteriorates
Solution Approach 1:
The patent extracts the high-voltage measurement function from the chuck stage and relocates it to a dedicated measurement electrode positioned close to the device under test. This separates the wafer holding function (chuck stage) from the high-voltage measurement function (measurement electrode), allowing the measurement electrode to be positioned optimally near the device while the chuck stage can be positioned independently. This extraction eliminates the need for long cables connecting the chuck stage to the evaluation unit, thereby reducing parasitic inductance and improving evaluation accuracy.
2Reliability
If the chuck stage and probe contact region are made large in area, then they can securely hold and contact the semiconductor wafer, but insulation becomes more difficult to secure at high voltages
Solution Approach 1:
The patent segments the wafer contact interface into separate functional regions: the chuck stage for mechanical holding and the measurement electrode for electrical contact. By dividing these functions into spatially separated components, each component can be optimized independently - the chuck stage can be large for stable holding while the measurement electrode can be small to minimize high-voltage area and facilitate insulation. This segmentation resolves the contradiction between reliable wafer holding and insulation at high voltages.
Solution Approach 2:
The patent applies local quality by making the measurement electrode small and localized only where electrical contact with the device under test is required, rather than using a large chuck stage for both mechanical and electrical functions. This localized approach minimizes the high-voltage area to only what is absolutely necessary for measurement, thereby facilitating insulation while maintaining reliable wafer holding through the separate chuck stage.
3Ease of operation
If the measurement path is lengthened to accommodate component positioning, then components can be properly positioned, but parasitic inductance increases and affects measurement accuracy
Solution Approach 1:
The patent introduces a dedicated measurement electrode as an intermediary component between the device under test and the evaluation unit. This intermediary allows the measurement function to be positioned optimally close to the device, minimizing the measurement path length and parasitic inductance, while the chuck stage and other components can be positioned independently without affecting the measurement path. The measurement electrode acts as a mediator that decouples the positioning requirements of different components.
Data Source
AI summary
A back surface potential lead-out portion has one end portion disposed in a side of a back surface of a semiconductor wafer held by a semiconductor wafer holding portion and the other end portion disposed in a side of a front surface of the semiconductor wafer held by the semiconductor wafer holding portion. The semiconductor wafer and the semiconductor wafer holding portion that holds the semiconductor wafer are movable in an in-plane direction of the semiconductor wafer. In a case where the semiconductor wafer and the semiconductor wafer holding portion that holds the semiconductor wafer are moved in the in-plane direction, a portion of the back surface potential lead-out portion located in the in-plane direction from the semiconductor wafer is fixed close to the outside of a movement region of the semiconductor wafer.