Semiconductor Device with Exposed Gate Lead Frames
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Power converters for hybrid and electric cars face challenges in suppressing temperature rise and reducing size while achieving high output and low loss.
Innovation Solution
A semiconductor device configuration with a first and second power semiconductor element, lead frames, and a sealing member with exposed gate lead frames, allowing for efficient heat dissipation and reduced size through shared gate lead frames and strategic placement of lead frames for thermal interference reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple power semiconductor elements are connected in parallel to achieve higher current output, then the current handling capability is improved, but the device size and thermal management complexity increase
Solution Approach 1:
Multiple gate lead frames are connected and integrated into a single common gate lead frame structure. This merging approach allows multiple power semiconductor elements to share a common gate control path, reducing the overall number of separate lead frames and interconnections needed, thereby achieving higher current capability without proportionally increasing device size
Solution Approach 2:
The common gate lead frame serves multiple functions simultaneously: it provides gate control signals to multiple power semiconductor elements, acts as a current return path, and functions as a structural support element. This multi-functionality reduces the number of dedicated components needed, allowing higher current output without proportional size increase
2Volume of stationary object
If power semiconductor elements are arranged in a compact configuration to reduce device size, then the volume is reduced, but thermal interference between elements increases
Solution Approach 1:
The lead frames are positioned and configured with specific local characteristics: gate lead frames are placed adjacent to power semiconductor elements they control, while power lead frames are positioned to provide optimal current paths. This localized optimization of lead frame placement and configuration enables compact arrangement while maintaining adequate thermal separation and heat dissipation pathways between elements
3Device complexity
If a single gate lead frame is used to control multiple power semiconductor elements, then the device complexity is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
Multiple gate lead frames are pre-connected and integrated into a common gate lead frame structure before the final assembly step. This preliminary integration establishes the gate control architecture in advance, allowing subsequent assembly steps to work with a pre-defined, rigid structure that is easier to position and connect to power semiconductor elements with standard tolerances
Data Source
AI summary
To suppress a temperature rise of a chip accompanying a production of large output by a power converter, and to reduce a size of the power converter. A power semiconductor device includes: a first power semiconductor element to configure an upper arm of an inverter circuit; a second power semiconductor element to configure a lower arm of the inverter circuit; a first lead frame to transmit power to the first power semiconductor element; a second lead frame to transmit power to the second power semiconductor element; a first gate lead frame to transmit a control signal to the first power semiconductor element; and a sealing member to seal the first power semiconductor element, the second power semiconductor element, the first lead frame, the second lead frame, and the first gate lead frame. In the power semiconductor device, a through-hole is formed in the sealing member, and a part of the first gate lead frame and a part of the second lead frame are exposed to an inner peripheral surface of the through-hole.