Semiconductor Extension Region Strain Engineering
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Solution Overview
Problem
Current semiconductor device manufacturing faces challenges in scaling to single-digit nanometer nodes, particularly in creating three-dimensional devices with transistors stacked on top of each other, as existing two-dimensional fabrication methods become less effective.
Innovation Solution
The introduction of a semiconductor device with a gate structure featuring a gate spacer and a channel with a recessed extension region made of a different material composition, providing strain to enhance performance, along with p-type and n-type lateral nanowires stacked vertically and connected through specific openings in the gate spacer, and extension doping of silicon germanium to improve access and strain within the nanowires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional fabrication methods are used to scale semiconductor devices, then manufacturing simplicity is maintained, but device performance and transistor density are limited
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional vertically stacked transistors. Multiple transistor layers are stacked above the substrate, with gate structures extending vertically and channels arranged in three-dimensional configurations. This dimensional change enables significantly higher transistor density per unit area while maintaining compatibility with existing fabrication processes through adapted deposition and etching sequences.
2Productivity
If three-dimensional vertically stacked transistors are implemented, then transistor density is increased, but fabrication complexity increases
Solution Approach 1:
The three-dimensional transistor structure is segmented into distinct functional layers: substrate layer, first transistor layer, second transistor layer, and interlayer dielectric regions. Each layer is formed through separate fabrication sequences, allowing independent optimization and control. The gate structures, channels, and source/drain regions are segmented and formed in a bottom-up approach, simplifying the overall fabrication process despite the vertical stacking.
Solution Approach 2:
The fabrication process employs preliminary actions by first forming the substrate and first transistor layer completely, including gate structures and source/drain regions, before proceeding to form the second transistor layer. Gate spacers and mandrels are formed in advance to define subsequent layer patterns. This sequential preliminary formation reduces process complexity compared to simultaneous multi-layer fabrication.
3Length of moving object
If channel dimensions are reduced for scaling, then device size is decreased, but drive current and performance are reduced
Solution Approach 1:
The patent compensates for reduced channel length by introducing vertical stacking, where multiple transistor layers are stacked above each other. The total effective channel width is increased through the cumulative width of channels across multiple vertical layers. This three-dimensional approach maintains high drive current despite individual channel lengths being scaled down to single-digit nanometers.
Solution Approach 2:
The patent employs composite material structures in the channel regions, including semiconductor materials with different bandgaps and strain-engineered material compositions. The channel may include strained silicon or III-V semiconductor materials that enhance carrier mobility, compensating for the reduced channel length and maintaining drive current performance in scaled devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased strain and performance in semiconductor devices by forming extension regions within the gate spacer, allowing for enhanced drive current and improved scaling capabilities in three-dimensional device fabrication.
Implementation Method 1
an extension region is in contact with the end of the channel within the recess, the extension region being formed of an extension material having a different composition than a channel material of the channel such that a strain is provided in the channel
Data Source
AI summary
A semiconductor device herein includes doped extension regions for silicon and silicon germanium nanowires. The nanowires can be selectively grown and recessed into a gate spacer. The semiconductor device can include a gate structure including the gate spacer; the nanowire or channel extending through the gate structure such that an end of the channel is recessed within a recess in said gate spacer; an extension region in contact with the end of the channel within the recess, the extension region being formed of an extension material having a different composition than a channel material of the channel such that a strain is provided in the channel; and a source-drain contact in contact with the extension region and adjacent to the gate structure.