Semiconductor Fabrication Using Self-Aligned Multiple Patterning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing integration of semiconductor devices has led to challenges in reducing pattern widths and spaces, resulting in deteriorated deposition and etching processes, which affect the reliability of semiconductor devices due to increased pattern heights and aspect ratios.
Innovation Solution
A method for fabricating semiconductor devices involves forming specific patterns and layers on a substrate, using etch masks and spacer layers to create trenches, and selectively etching to define active regions with insulating material, improving process efficiency and reducing fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pattern widths and spaces are reduced to increase integration, then device integration is improved, but deposition and etching processes deteriorate
Solution Approach 1:
The patent divides the pattern formation process into multiple stages using self-aligned multiple patterning (SAMP). Instead of forming all patterns in a single step, it segments the process into sequential deposition and etching steps with intermediate spacer formation, allowing each step to work on larger, more controllable dimensions while achieving finer final pattern dimensions.
Solution Approach 2:
The patent transitions from planar pattern definition to three-dimensional structure formation by creating mandrels and spacers with significant height differences. This vertical dimension provides additional process margin, as the etch selectivity between different materials and the height of sacrificial layers enable precise pattern transfer even when lateral dimensions are reduced.
2Productivity
If pattern widths are reduced to increase integration, then device integration is improved, but pattern heights and aspect ratios increase
Solution Approach 1:
The patent segments the pattern formation into multiple deposition steps with intermediate etching, where each step creates partial structures that are subsequently refined. This avoids the need to form complete high aspect ratio patterns in a single step, distributing the dimensional challenge across multiple manageable steps.
Solution Approach 2:
The patent performs preliminary pattern formation using spin-on-glass (SOG) layers and mandrels before final trench formation. These preliminary structures serve as self-aligned masks and spacers, pre-defining the pattern locations and reducing the aspect ratio requirements for subsequent etching steps by providing structural support and alignment references.
3Productivity
If conventional patterning methods are used with reduced dimensions, then device integration is improved, but process control deteriorates
Solution Approach 1:
The patent employs self-aligned multiple patterning where previously formed structures automatically serve as alignment references for subsequent steps. The spacers and mandrels formed in earlier steps self-align the next deposition and etching operations, eliminating the need for additional photolithography alignment steps and providing inherent process control through material selectivity and geometric constraints.
Solution Approach 2:
The patent changes the fundamental parameters of the patterning process by transitioning from photolithography-based lateral definition to deposition-based vertical definition. It uses etch selectivity between different materials (SOG, mandrel, spacer, substrate) as the controlling parameter instead of optical resolution, providing better process control through material property differences rather than dimensional constraints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the reliability of semiconductor devices by maintaining process control and reducing fabrication costs through efficient trench formation and active region definition, addressing the challenges of increased pattern heights and aspect ratios.
Implementation Method 1
forming cell spacers on outer sidewalls of the pillars to define second holes
Implementation Method 2
etching the substrate using the cell spacers, the first cell patterns, and the peripheral pattern as etch masks to form a trench
Data Source
AI summary
A method of fabricating a semiconductor device includes forming first cell patterns on a substrate, forming a first layer relative to the first cell patterns, and forming a second cell pattern and a peripheral pattern on the first layer. The second cell pattern includes first holes in a cell region and the peripheral pattern is located in a peripheral region. The method also includes filling the first holes, removing the second cell pattern to expose pillars, and forming second holes. Each of the second holes corresponds to adjacent cell spacers of the pillars. The method also includes removing the pillars to form third holes corresponding to respective ones of the cell spacers, and etching the substrate using the cell spacers, the first cell patterns, and the peripheral pattern as etch masks to form a trench.