Semiconductor Device Face-Down Mounting Heat Dissipation
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Solution Overview
Problem
The challenge is to reduce the size of power amplifier modules in cellular phones while maintaining their functions and enhancing heat radiation efficiency, as existing technologies face difficulties in effectively connecting semiconductor chips with compound semiconductors to silicon-based wiring substrates, leading to inferior thermal conductivity and increased costs due to the need for thinner chips.
Innovation Solution
A semiconductor device with a first semiconductor chip containing HBTs mounted face-down on a wiring substrate, where the emitter bump electrode connects emitter electrodes to via holes in the substrate, allowing direct heat conduction and radiation, and a second semiconductor chip is mounted face-up for efficient heat dissipation, enabling reduced module size and improved thermal efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If compound semiconductor chips are mounted face-up on silicon-based wiring substrates, then electrical connection is achieved, but heat radiation efficiency is inferior due to poor thermal conductivity at the interface
Solution Approach 1:
The patent inverts the conventional mounting orientation by mounting the compound semiconductor chip face-down on the silicon substrate. This allows the high-heat-generating HBTs to be in direct thermal contact with the silicon substrate, which has superior thermal conductivity, thereby efficiently conducting heat away from the active devices.
Solution Approach 2:
The patent introduces an adhesive layer as a thermal intermediary between the compound semiconductor chip and the silicon substrate. This adhesive layer serves as a thermal bridge that enhances heat transfer from the chip to the substrate while maintaining electrical isolation where needed.
2Reliability
If wire bonding is used to connect semiconductor chips and wiring substrates, then electrical connection is achieved, but module size increases due to required wire bond regions
Solution Approach 1:
The patent merges the electrical connection function with the mechanical mounting function by using bump electrodes that directly contact via holes in the substrate. This eliminates the need for separate wire bonding operations and reduces the space required for connection regions.
Solution Approach 2:
The patent transitions from planar wire bonding connections to three-dimensional vertical connections through bump electrodes and via holes. This dimensional change allows connections to be made in the thickness direction of the substrate, reducing the lateral space required for connections and enabling smaller module size.
3Temperature
If semiconductor chip thickness is reduced to improve heat radiation, then manufacturing cost increases and handling becomes difficult
Solution Approach 1:
The adhesive layer acts as a thermal intermediary that enables effective heat transfer without requiring the chip itself to be extremely thin. The heat conduction path extends through the adhesive layer to the silicon substrate, allowing the chip to maintain sufficient thickness for easy handling while still achieving good heat radiation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances heat radiation efficiency and allows for a reduction in semiconductor chip thickness, reducing costs and improving handling, while also enabling a smaller power amplifier module size without compromising performance.
Implementation Method 1
the emitter bump electrode connects emitter electrodes to via holes in the substrate, allowing direct heat conduction and radiation
Data Source
AI summary
A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip.