Semiconductor Fail Location Detection via Data Bus Inversion
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Solution Overview
Problem
As the number of bits with phase changes increases in semiconductor devices, the occurrence of simultaneous switching noise (SSN) and inter symbol interface (ISI) phenomena also increases, necessitating methods to reduce these issues and ensure reliable data transmission.
Innovation Solution
A semiconductor system that includes a memory circuit and a data processing circuit, which performs a data bus inversion operation and a test operation mode to detect fail locations by comparing pattern data with read data and generating fail location information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the number of bits with phase changes is increased to improve data transmission speed, then the operating speed is improved, but the occurrence of SSN and ISI phenomena increases
Solution Approach 1:
The patent applies data bus inversion operation where the data bits are inverted before transmission. When a phase change occurs in the data stream, the inversion operation flips the bits, which reverses the phase change effect. This reduces the number of consecutive phase changes and thereby decreases the occurrence of SSN and ISI phenomena while maintaining high data transmission speed
2Object-affected harmful factors
If data bus inversion operation is performed to reduce SSN and ISI phenomena, then the harmful factors are reduced, but the device complexity increases
Solution Approach 1:
The semiconductor device performs the data bus inversion operation autonomously without requiring external control signals or additional complex control logic. The inversion is implemented through self-clocking mechanisms and automatic phase detection within the device itself, which simplifies the overall system architecture while still effectively reducing SSN and ISI phenomena
3Reliability
If test operation mode is added to detect fail locations, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The test operation mode shares the same hardware infrastructure (data processing circuit, memory circuit, and bus structures) used for normal data transmission operations. The fail location detection functionality is integrated into the existing data path, allowing the same circuits to serve both transmission and testing purposes. This multi-functionality approach improves reliability through comprehensive testing while minimizing the increase in device complexity
4Productivity
If multiple bits are input/output every clock cycle to increase operating speed, then the productivity is improved, but the probability of transmission errors increases
Solution Approach 1:
The patent performs preliminary inversion of data bits before transmission, which prepares the data stream in a way that reduces phase changes during transmission. This preliminary action helps prevent transmission errors from occurring in the first place, thereby maintaining high productivity while improving reliability through proactive error prevention rather than reactive error correction
Data Source
AI summary
A semiconductor device includes a memory circuit including a plurality of mats and configured to output first read data having a data sequence identical to a data sequence of pattern data after the start of a read operation during a test operation mode operation and configured to output a fail address including error information of the first read data, and a data processing circuit configured to output the first read data as data and configured to generate fail location information by encoding the fail address.