Semiconductor Apparatus Fail Flag Generation for Redundancy Cell Management
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Solution Overview
Problem
Current semiconductor systems face challenges in effectively managing and utilizing redundancy memory cells, which are crucial for replacing defective normal memory cells, leading to reliability and durability issues.
Innovation Solution
A semiconductor system comprising a normal memory cell array, a redundancy memory cell array, a fail information control circuit, and a register array that generates and outputs a fail flag based on the number of fail bits in read data, allowing for the storage of corresponding addresses in specific register groups to prioritize the use of more reliable redundancy memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy memory cells are used to replace defective normal memory cells, then reliability of the semiconductor apparatus is improved, but effective management and utilization of redundancy memory cells becomes more complex
Solution Approach 1:
The patent applies parameter changes by categorizing redundancy memory cells based on the number of fail bits (0, 1, 2, or 3 or more) and assigning them to different register groups accordingly. This parameter-based classification simplifies the management complexity while maintaining high reliability, as the host can selectively use redundancy cells with fewer fail bits preferentially.
Solution Approach 2:
The patent implements local quality by creating different register groups with different qualities based on their fail bit counts. Each register group serves a specific purpose: register group 0 for perfect redundancy cells, register group 1 for cells with one fail bit, register group 2 for cells with two fail bits, and register group 3 for cells with three or more fail bits. This localized quality differentiation enables effective management while improving overall system reliability.
2Device complexity
If all redundancy memory cells are treated equally, then device complexity is reduced, but reliability and durability of the semiconductor apparatus decreases
Solution Approach 1:
The patent resolves this contradiction by introducing a parameter-based differentiation system where redundancy memory cells are classified according to their fail bit counts. This creates multiple register groups (0-3) with different qualities, allowing the system to maintain simplicity in structure while achieving high reliability through selective usage based on cell quality parameters.
Solution Approach 2:
The patent applies preliminary action by pre-classifying redundancy memory cells into different register groups based on their fail bit characteristics before actual use. This preliminary classification enables the host to automatically select the most reliable redundancy cells when repairing defective normal memory cells, thereby improving durability without increasing operational complexity.
3Device complexity
If redundancy memory cells with more fail bits are used preferentially, then device complexity is reduced, but reliability of the semiconductor apparatus deteriorates
Solution Approach 1:
The patent implements preliminary action by pre-organizing redundancy memory cells into distinct register groups based on their quality (fail bit count) before the repair process begins. This preliminary arrangement enables the host to systematically select redundancy cells with fewer fail bits first, ensuring high reliability replacements while maintaining a simple and automated selection process without complex real-time evaluations.
Data Source
AI summary
A semiconductor system according to an embodiment includes: a semiconductor system including a normal memory cell array and a redundancy memory cell array for repairing a defective cell among memory cells within the normal memory cell array, and configured to output to an external a fail flag generated according to a number of fail bits within read data output from the redundancy memory cell array; and a host configured to store an address corresponding to the read data into a selected register group from among a plurality of register groups, the selected register group being matched to the fail flag.