Superimposed Image Generation for Semiconductor Failure Analysis
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Solution Overview
Problem
The miniaturization and integration of semiconductor devices have made it difficult for conventional semiconductor inspection apparatuses to efficiently analyze failure parts, as they struggle to quickly and accurately relate observed images to layout data.
Innovation Solution
A semiconductor failure analysis apparatus and method that acquires pattern and layout images, generates a superimposed image with variable transmittance, allowing for efficient failure analysis by relating observed images to layout information, thereby improving analysis efficiency and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional semiconductor inspection apparatus are used for miniaturized and integrated semiconductor devices, then the existing analysis methods can be applied, but the analysis efficiency and speed deteriorate due to difficulty in quickly identifying failure parts
Solution Approach 1:
The patent merges the observed image and layout image into a single superimposed display, allowing simultaneous visualization of both images. This integration enables analysts to quickly correlate observed failures with their corresponding layout positions without switching between separate displays, thereby improving analysis efficiency while maintaining accuracy
Solution Approach 2:
The layout image serves as an intermediary that bridges the observed image and the physical structure of the semiconductor device. By superimposing the layout image on the observed image, the system provides a visual mediator that helps analysts quickly identify failure parts by correlating observed anomalies with their corresponding circuit layout positions
2Reliability
If the observed image and layout image are displayed separately, then each image can be clearly viewed, but the correlation between observed failures and layout positions becomes difficult to identify
Solution Approach 1:
The patent combines the observed image and layout image into a superimposed display where both images are shown together in one view. This merging allows analysts to maintain clear identification of features from both images while simultaneously establishing correlations between observed failures and their corresponding layout positions, eliminating the need to switch between separate displays
3Reliability
If both observed image and layout image are displayed with full opacity, then both images are clearly visible, but the superimposed details become difficult to distinguish
Solution Approach 1:
The patent applies different transparency properties to different regions or layers of the superimposed image, allowing certain areas to be more transparent than others. This local quality adjustment ensures that both the observed image and layout image remain clearly visible while preserving the visibility of superimposed details in critical regions
Solution Approach 2:
The system allows dynamic adjustment of transparency parameters for the superimposed images. By changing the transparency parameter, users can optimize the display to clearly see both the observed image and layout image simultaneously, ensuring that superimposed details remain distinguishable while maintaining overall image visibility
Data Source
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Figure 3(a)~3(c)
AI summary
A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring at least a pattern image P1 of a semiconductor device, a layout information acquirer 12 for acquiring a layout image P3, a failure analyzer 13 for analyzing a failure of the semiconductor device, and an analysis screen display controller 14 for letting a display device 40 display information about the failure analysis. The analysis screen display controller 14 generates a superimposed image in which the pattern image P1 and the layout image P3 are superimposed, as an image of the semiconductor device to be displayed by the display device 40, and sets a transmittance of the layout image P3 relative to the pattern image P1 in the superimposed image. This substantializes a semiconductor failure analysis apparatus, analysis method, analysis program, and analysis system capable of securely and efficiently carrying out the analysis of the failure of the semiconductor device.