Semiconductor Failure Analysis via Equipotential Interconnection Tracing
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Solution Overview
Problem
Conventional semiconductor failure analysis tools face challenges in accurately and efficiently analyzing miniaturized and integrated semiconductor devices, as they struggle to pinpoint failure parts within complex interconnection networks.
Innovation Solution
A semiconductor failure analysis apparatus and method that acquires failure observed images and layout information, sets analysis regions based on reaction information, and uses interconnection information to perform equipotential tracing, extracting candidate interconnections as potential failure points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional inspection apparatus are used for miniaturized semiconductor devices, then the analysis capability is maintained, but the ability to pinpoint failure parts deteriorates due to increased complexity and miniaturization
Solution Approach 1:
The patent segments the complex interconnection network analysis by introducing layout information that divides the device into functional blocks and interconnection layers. The analysis apparatus separately acquires device layout information showing interconnection patterns and combines it with failure observed images, allowing systematic segmentation of the analysis process to handle complexity while maintaining precision in identifying failure parts.
2Measurement precision
If detailed analysis of all interconnections is performed, then measurement precision is improved, but analysis time and productivity deteriorate
Solution Approach 1:
The patent extracts only the relevant interconnection information needed for failure analysis by acquiring layout information that specifically shows interconnection patterns associated with the failure observed image. Instead of analyzing all interconnections in the device, the system extracts and analyzes only those interconnections that correspond to the observed failure reactions, significantly improving analysis efficiency while maintaining precision.
Solution Approach 2:
The patent performs preliminary acquisition of layout information before conducting the actual failure analysis. By having the interconnection pattern data ready in advance, the system can quickly map failure observed images to specific interconnections without performing exhaustive searches during the analysis phase, thereby improving productivity while maintaining accurate identification.
3Reliability
If comprehensive layout information is acquired, then analysis reliability is improved, but data processing complexity and time increase
Solution Approach 1:
The patent applies local quality by acquiring and processing layout information specifically for the region shown in the failure observed image, rather than processing the entire device layout. The system focuses computational resources on the local area where failure reactions are observed, maintaining high analysis reliability for the critical region while minimizing overall data processing time.
Data Source
AI summary
A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, and a failure analyzer 13 for analyzing a failure. The failure analyzer 13 extracts as a candidate interconnection for a failure, an interconnection passing an analysis region, out of a plurality of interconnections, using interconnection information to describe a configuration of interconnections in the semiconductor device by a pattern data group of interconnection patterns in respective layers, and, for extracting the candidate interconnection, it performs an equipotential trace of the interconnection patterns using the pattern data group, thereby extracting the candidate interconnection. This substantializes a semiconductor failure analysis apparatus, failure analysis method, and failure analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device using the failure observed image.