Semiconductor Failure Rate Prediction Using Multi-Stage Soft Error Simulation
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Solution Overview
Problem
The reduction in size of semiconductor devices, such as DRAM and SRAM, has made it increasingly difficult to maintain high reliability against soft errors caused by alpha rays and neutron beams, leading to data inversion and other failures.
Innovation Solution
A method involving the use of schematic and design simulation tools to generate a netlist, perform simulations on layout data, and calculate failure rates by analyzing cross-sectional areas affected by high-energy particles, allowing for precise prediction of semiconductor device failure rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of semiconductor devices is reduced to increase integration density, then the degree of integration is improved, but reliability against soft errors deteriorates
Solution Approach 1:
The patent segments the analysis process into multiple simulation stages (circuit-level simulation, device-level simulation, and particle injection simulation) to comprehensively evaluate soft error susceptibility. This segmentation allows for detailed analysis of different failure mechanisms while maintaining overall system reliability assessment.
Solution Approach 2:
The patent performs preliminary simulations using circuit simulation tools to identify critical nodes and paths before conducting more complex device-level simulations. This preliminary action reduces computational resources required while maintaining prediction accuracy by focusing analysis on high-risk areas.
2Device complexity
If conventional simulation methods are used, then the prediction process is simple, but prediction precision of failure rate deteriorates
Solution Approach 1:
The patent merges multiple simulation tools and methodologies (circuit simulation, device simulation, and particle physics simulation) into an integrated prediction system. This combination enables comprehensive failure rate prediction by considering both circuit-level and device-level effects, achieving high precision without excessive complexity through systematic integration.
Solution Approach 2:
The patent introduces an intermediary conversion process that translates simulation results from different tools into a unified failure rate metric. This intermediary layer harmonizes data from various simulation sources, enabling accurate prediction while managing the complexity of multi-tool integration.
Data Source
AI summary
A method of predicting semiconductor device failure rate and an electronic device for performing the method are provided. The method of predicting semiconductor device failure rate includes receiving schematic data for a unit circuit in a first circuit and layout data corresponding to the schematic data, generating, by at least one processor, a netlist based on the schematic data and the layout data, performing a first simulation on the layout data to generate first simulation data for a test point of the layout data corresponding to a first node in the netlist, applying the first simulation data to a second simulation for the first node to generate second simulation data regarding whether the unit circuit is in fail operation, and calculating a failure rate for the first circuit based on the second simulation data.