Semiconductor Failure Rate Evaluation via ECC Coefficient
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Solution Overview
Problem
Conventional methods for evaluating the failure rate of semiconductor chips with error checking and correcting functions are time-consuming and costly, requiring a large number of chips to be tested to achieve accurate results.
Innovation Solution
A method involving a first read-write test with error checking and correcting functions turned off, followed by an aging test and a second read-write test, calculates failure rates using first and second failure bit counting values and an error checking and correcting coefficient to determine the reliability of semiconductor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If each memory chip is used as an evaluating unit with conventional testing methods, then the failure rate evaluation is accurate, but the number of chips required for testing is huge and the testing process is time-consuming
Solution Approach 1:
The patent segments the evaluation process into two distinct phases: an initial read-write test phase and a subsequent aging test phase. By dividing the testing into segments with different sample sizes and purposes, the method achieves accurate failure rate evaluation without requiring huge numbers of chips throughout the entire process. The initial phase uses a smaller set of chips to establish baseline failure rates, while the aging phase focuses on detecting changes in those same chips.
Solution Approach 2:
The patent performs preliminary testing (first read-write test) before the main aging evaluation. This preliminary action establishes baseline failure bit counting values for each chip, which are then used as reference points during the aging process. This allows the method to detect changes and calculate failure rates without needing to test every chip from scratch during the aging phase.
2Reliability
If more than 4000 memory chips are tested to achieve 32 DPPM failure rate requirement, then the failure rate evaluation is accurate, but the testing cost and time are significantly increased
Solution Approach 1:
The patent employs dynamic testing strategies where the evaluation process adapts based on results from the initial read-write test. Chips are selected for aging based on their initial performance characteristics, and the aging duration and intensity are adjusted according to the observed failure patterns. This dynamic approach allows accurate reliability evaluation with fewer chips and less time compared to static conventional methods that test all chips uniformly.
Solution Approach 2:
The patent changes key testing parameters between phases: the error checking and correcting coefficient is calculated differently based on whether the chip passed or failed the initial read-write test, and the aging conditions are optimized based on initial failure bit counts. These parameter changes allow the system to focus resources on chips that most contribute to failure rate evaluation, reducing the total number of chips and time required.
3Reliability
If conventional testing methods are used for high density memory chips, then the reliability evaluation is thorough, but the evaluating cost is high
Solution Approach 1:
The patent uses the initial read-write test results as a 'copy' or proxy for predicting aging performance. Rather than performing exhaustive aging tests on all chips, the method uses the baseline failure bit counting values from the initial test to identify which chips are most likely to fail during aging. This copying approach maintains thorough reliability evaluation while significantly reducing the number of expensive aging tests needed.
Solution Approach 2:
The patent treats the initial read-write test as a disposable screening phase where chips that fail are discarded from further expensive aging testing. By using a cheaper, faster initial test to eliminate obviously defective chips, the method reduces the number of chips that need to undergo costly and time-consuming aging tests, thereby lowering overall evaluation costs while maintaining thoroughness.
Data Source
AI summary
A method for evaluating failure rate, which is applied to a plurality of semiconductor chips with error checking and correcting function includes the following steps. A first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of first failure bit counting values. The error checking and correcting function of each of the semiconductor chips is off. An aging test is applied to the semiconductor chips. A second read-write test operation as the first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of second failure bit counting values. The number of the semiconductor chips, the first failure bit counting values, the second failure bit counting values and an error checking and correcting coefficient are calculated to obtain a failure rate of the semiconductor chips.