Semiconductor Fault Analysis Using Simulation Data and Double Sampling
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Solution Overview
Problem
As semiconductor manufacturing processes become more complex, identifying and classifying faults in semiconductor devices in a timely and reliable manner is challenging due to increasing complexity and integration, especially when pre-training data is insufficient.
Innovation Solution
A semiconductor fault analysis device and method that uses a combination of measurement data, simulation data, and deep neural networks to classify faults, where a simulator generates simulation data for various fault types and a classifier performs analysis using a training model based on this data, even when pre-training data is insufficient, and employs double sampling to improve classification accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If simulation data is used instead of measurement data for training, then the availability of training data is improved, but the measurement precision may be degraded
Solution Approach 1:
The patent creates a virtual copy of the measurement environment through simulation. A circuit simulation model replicates the electrical characteristics and fault behaviors of the actual semiconductor device, generating synthetic measurement data that mirrors real-world scenarios without requiring physical samples. This copying approach enables training data generation when physical measurement data is unavailable.
Solution Approach 2:
The patent performs preliminary fault injection in the simulation model before actual measurements are taken. By pre-introducing various fault conditions into the simulation circuit, the system generates training data covering all possible fault scenarios in advance, ensuring comprehensive training coverage without needing to physically create faulty semiconductor devices.
2Reliability
If double sampling is performed to improve classification accuracy, then the reliability of fault analysis is improved, but the analysis time is increased
Solution Approach 1:
The patent implements a staged sampling strategy where the first sampling performs basic fault detection and the second sampling performs detailed classification only when needed. This partial action approach applies the full double sampling process selectively rather than universally, maintaining high accuracy for critical cases while reducing overall analysis time for routine inspections.
Solution Approach 2:
The system uses feedback from the first sampling result to control whether the second sampling is executed. When the first sampling confidently identifies a fault type, the system skips the second sampling, thereby reducing analysis time. When uncertainty exists, the feedback mechanism triggers the second sampling to improve accuracy, creating an adaptive time-accuracy balance.
Data Source
AI summary
A fault analysis method of a semiconductor fault analysis device is provided. The fault analysis method includes: receiving measurement data measured corresponding to a semiconductor device; generating double sampling data based on the measurement data and reference data; performing a fault analysis operation with respect to the double sampling data; classifying a fault type of the semiconductor device based on a result of the fault analysis operation; and outputting information about the fault type.