Semiconductor Fault Detection via Secondary Node Lists
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Solution Overview
Problem
Current fault detection methods in semiconductor devices are inefficient in identifying defects, particularly in regions with high defect densities, as they require extensive test patterns and do not effectively target clustered defects in neighbor nodes.
Innovation Solution
A method involving the generation of filtered test pattern sets using primary and secondary node lists, where secondary node lists are derived from primary nodes within a predetermined distance, allowing for targeted fault detection and reducing the number of test patterns needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional fault detection methods are used, then all possible faults can be detected, but the test pattern count becomes excessively large and detection efficiency decreases
Solution Approach 1:
The patent applies local quality by creating secondary node lists that identify specific regions with high defect densities within the semiconductor device. Instead of uniformly testing all nodes, the method focuses test patterns on localized areas where defects are more likely to occur, thereby maintaining high detection coverage while reducing the overall test pattern count.
Solution Approach 2:
The patent segments the fault detection process into two stages: first generating a comprehensive test pattern set, then filtering it to create a second test pattern set focused on high-defect-density regions. This segmentation allows the system to maintain thorough coverage while improving efficiency by concentrating resources on critical areas.
2Reliability
If comprehensive test patterns are generated to cover all faults, then detection coverage is maximized, but the complexity of the testing process increases
Solution Approach 1:
The patent applies preliminary action by pre-identifying high-defect-density regions through secondary node lists before generating the final test pattern set. This preliminary analysis allows the system to streamline the testing process by focusing only on critical areas, thereby reducing testing complexity while maintaining comprehensive coverage of important faults.
Solution Approach 2:
The patent changes the parameter of test pattern selection by using defect density as a filtering criterion. Instead of treating all nodes equally, the system adjusts test pattern generation based on the defect density parameter, creating a more efficient testing process that adapts to the actual characteristics of the semiconductor device.
3Productivity
If test patterns are reduced to improve efficiency, then detection speed increases, but the ability to detect clustered defects in neighbor nodes decreases
Solution Approach 1:
The patent applies local quality by creating secondary node lists that specifically identify neighbor nodes within a predetermined distance of each primary node. This local focus ensures that test patterns are generated to detect clustered defects in high-defect-density regions, maintaining detection precision while reducing the overall test pattern count through targeted testing.
Data Source
AI summary
A method of detecting one or more faults in a semiconductor device that includes generating a first test pattern set from a primary node list and a fault list. The primary node list includes one or more nodes and the fault list identifies one or more faults. The method also includes generating one or more secondary node lists from the primary node list and generating a second test pattern set from at least the first test pattern set and the secondary node list. Each node of the one or more nodes of the primary node list is associated with a corresponding secondary node list of the one or more secondary node lists.