Hierarchical Semiconductor Fault Injection via Status Register

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Solution Overview

Problem

Existing semiconductor devices face challenges in efficiently detecting failures in failure detection mechanisms and transmission paths, leading to prolonged test times when multiple error detection circuits are involved, which is not feasible in high-reliability systems requiring rapid fault injection testing.

Innovation Solution

A semiconductor device with a hierarchical module structure and an error control module that includes a status register to record failure statuses and an error injection function to output error signals, allowing for fault injection tests across multiple failure detection mechanisms in a short time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a large number of error detection circuits are provided to ensure high reliability, then the coverage of failure detection is improved, but the test time becomes enormous

Engineering Contradiction:
Improvefailure detection coverageVSAvoidtest time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The semiconductor device is divided into functionally divided hierarchical modules, with each module having its own failure detection mechanism. This segmentation allows parallel testing of multiple modules simultaneously, reducing the overall test time while maintaining comprehensive failure detection coverage across the entire device.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The error injection function is designed to universally inject error signals into multiple failure detection mechanisms through a shared status register. This multi-functional capability allows a single error injection unit to test numerous detection circuits in parallel, significantly reducing test time without sacrificing detection thoroughness.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Speed

If error signals are injected directly into failure detection mechanisms, then the injection speed is improved, but the ability to detect failures in transmission paths is lost

Engineering Contradiction:
Improveerror injection speedVSAvoidtransmission path failure detection
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The status register serves as an intermediary component between the error injection function and the failure detection mechanisms. Error signals are injected into the status register first, then propagated to the hierarchical modules. This intermediary approach maintains fast injection speed while ensuring that transmission path failures are detected, as the status register itself becomes part of the testable transmission path.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If multiple error detection circuits are tested sequentially, then the test accuracy is maintained, but the productivity is reduced

Engineering Contradiction:
Improvefailure detection accuracyVSAvoidtesting throughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The device is segmented into independent hierarchical modules, each with its own failure detection mechanism that can operate independently. This segmentation enables parallel testing of multiple modules simultaneously, dramatically increasing testing throughput while maintaining the accuracy of individual failure detection through dedicated detection circuits for each module.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple failure detection mechanisms are merged into a unified hierarchical structure with a common error injection function and status register. This merging allows coordinated parallel operation of multiple detection circuits, achieving both high testing throughput and maintained detection accuracy through the organized hierarchical architecture.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10997043B2Semiconductor device, semiconductor systems and test-control methods for executing fault injection test on a plurality of failure detection mechanism
Publication Date: 2021.05.04 RENESAS ELECTRONICS CORP
  • US10997043B2 patent drawing
  • US10997043B2 patent drawing
  • US10997043B2 patent drawing

AI summary

A semiconductor device capable of executing fault injection test on a plurality of failure detection mechanism in a short time is provided. The semiconductor device 1 has a plurality of hierarchical modules and an error control module 100 for controlling errors in the plurality of hierarchical modules. Each hierarchical module has a safety mechanism to detect failures in the functions of the components that make up the hierarchical modules. The error control module 100 includes a status register 120 configured to record data indicative of the status of failure of each hierarchical module, and a fault injection function 110 that outputs an error signal to the status register 120 to perform fault injection test. The error signal is inputted into the safety mechanism via the status register 120.