Semiconductor FET Layout With Cover Metal Shielding for Gate Capacitance
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Solution Overview
Problem
In semiconductor devices with finger-shaped electrodes, the arrangement of unit FETs leads to increased gate resistance and parasitic capacitance, deteriorating high-frequency characteristics due to the proximity of drain and gate electrodes.
Innovation Solution
The semiconductor device incorporates a configuration with a first and second transistor unit, a gate wiring, and cover metal layers that project over the gate wiring, reducing parasitic capacitance by shielding electric fields between the gate and drain electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple unit FETs are arranged in an extending direction of the electrodes to increase device capacity, then the device can handle higher current and power, but the gate resistance and parasitic capacitance increase, deteriorating high-frequency characteristics
Solution Approach 1:
The device is divided into multiple independent transistor units (first transistor unit, second transistor unit, etc.) that are arranged in parallel. Each unit has its own source electrode, gate electrode, and drain electrode, allowing the device to handle higher total current while maintaining good high-frequency characteristics through the shielding effect of cover metal layers between adjacent units
Solution Approach 2:
Cover metal layers are introduced as intermediary structures between adjacent transistor units. These cover metal layers extend from the source electrode toward the gate wiring and act as shielding elements that reduce parasitic capacitance between the drain of one transistor and the gate wiring, thereby improving high-frequency characteristics while allowing multiple units to be closely arranged
2Area of stationary object
If transistor units are arranged closely to reduce device area, then space utilization is improved, but parasitic capacitance between drain and gate electrodes increases, deteriorating device performance
Solution Approach 1:
Cover metal layers are positioned between the drain electrode of one transistor unit and the gate wiring of adjacent units. These intermediary metal structures extend from the source electrode region toward the gate wiring and provide electrostatic shielding that reduces parasitic capacitance, enabling compact arrangement of transistor units without significant performance degradation
Solution Approach 2:
The cover metal layers extend in the vertical dimension (thickness direction) from the source electrode, creating a three-dimensional shielding structure. This vertical extension provides effective parasitic capacitance reduction while maintaining a compact planar footprint, allowing multiple transistor units to be closely arranged in the horizontal plane
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses gate-drain parasitic capacitance, thereby improving the high-frequency characteristics and stability of the semiconductor device.
Implementation Method 1
a first cover metal layer provided on and electrically connected to the first source electrode, at least an upper portion of the first cover metal layer projecting toward the gate wiring more than the first source electrode
Data Source
AI summary
A semiconductor device includes a substrate, a first transistor unit having a first drain electrode, a first gate electrode, and a first source electrode, a second transistor unit having a second source electrode, a second gate electrode, and a second drain electrode, a gate wiring provided between the first source electrode and the second source electrode and electrically connected to the first gate electrode and the second gate electrode, a first cover metal layer electrically connected to the first source electrode, at least an upper portion of the first cover metal layer projecting toward the gate wiring more than the first source electrode, and a second cover metal layer electrically connected to the second source electrode, at least an upper portion of the second cover metal layer projecting toward the gate wiring more than the second source electrode.