Semiconductor Field Electrode Trench Design for Stress Reduction
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Solution Overview
Problem
Existing semiconductor devices with thick vertically extending dielectric layers for voltage blocking face mechanical stress issues due to high voltage requirements, leading to defects and damage.
Innovation Solution
A method involving the formation of trenches in a dielectric layer on a semiconductor body, creating a dielectric mesa region and a field electrode trench, with the field electrode insulated by a dielectric layer, allowing for adjustable thickness and reduced mechanical stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick vertically extending dielectric layer is formed to withstand high voltages, then the voltage blocking capability is improved, but mechanical stress increases causing defects and damages
Solution Approach 1:
The patent divides the originally single thick dielectric layer into multiple thinner dielectric layers separated by intermediate layers. This segmentation reduces the mechanical stress in each individual dielectric layer while maintaining the overall voltage blocking capability through the cumulative thickness of all layers. The intermediate layers act as stress relief interfaces between the stacked dielectric layers.
Solution Approach 2:
The patent creates a composite structure by stacking multiple dielectric layers with different material properties and thicknesses. This composite approach allows optimization of each layer's thickness to minimize stress while ensuring the total stack provides the required voltage blocking. The different materials in the composite structure have varying mechanical and electrical properties that complement each other.
2Loss of energy
If the doping concentration of the drift region is increased, then the on-resistance is reduced, but the voltage blocking capability deteriorates
Solution Approach 1:
The drift region is divided into multiple segments with different doping concentrations arranged in series. Each segment has an optimized doping level that balances local current conduction and voltage blocking. The series arrangement of these doped segments allows the device to achieve low on-resistance through highly doped regions while maintaining high voltage blocking capability through the combined effect of all segments.
3Reliability
If the thickness of the field electrode dielectric is increased to withstand high voltages, then the voltage blocking capability is improved, but mechanical stress and risk of defects increase
Solution Approach 1:
The thick field electrode dielectric is divided into multiple thinner dielectric layers stacked in series. Each thin layer is easier to form with high precision and fewer defects compared to a single thick layer. The cumulative thickness of the stacked layers provides the required voltage blocking while each individual layer remains within manufacturable thickness limits.
Solution Approach 2:
The patent forms multiple thin dielectric layers in sequence, with each layer being deposited or grown under optimized conditions to ensure high quality and minimal defects. By building up the total dielectric thickness incrementally through multiple thin layers rather than forming one thick layer, the manufacturing process maintains higher precision and lower defect rates throughout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the production of semiconductor devices with thick dielectric layers that withstand high voltages without inducing mechanical stress, enhancing the voltage blocking capability and reliability of the devices.
Implementation Method 1
a field electrode or field plate is provided in the drift region, is dielectrically insulated from the drift region by a field electrode dielectric... A voltage across the field electrode dielectric is dependent on the magnitude of the voltage that is applied between the load terminals and that reverse biases the pn junction
Implementation Method 2
The doping concentration of the drift region is lower than the doping concentration of the further device region, so that a depletion region (space charge region) mainly expands in the drift region when the device blocks, which is when the pn junction is reverse biased
Implementation Method 3
The doping concentration of the drift region may be increased without reducing the voltage blocking capability of the device when charges are provided in the drift region that may act as counter charges to ionized dopant atoms in the drift region when the pn junction is reverse biased
Data Source
AI summary
A method of producing a semiconductor device includes providing a semiconductor body having a first surface and a dielectric layer arranged on the first surface and forming at least one first trench in the dielectric layer. The at least one first trench extends to the semiconductor body and defines a dielectric mesa region in the dielectric layer. The method further includes forming a second trench in the dielectric mesa region distant to the at least one first trench, forming a semiconductor layer on uncovered regions of the semiconductor body in the at least one first trench and forming a field electrode in the second trench.