Semiconductor Field Electrode Trenches for Defect Reduction

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Solution Overview

Problem

The challenge in manufacturing semiconductor devices lies in shrinking device dimensions and addressing high defect densities caused by large topographies, which complicate layer formation and structuring, leading to increased defect density and reduced yield.

Innovation Solution

A method involving the formation of a structured etch stop layer and a second insulation layer, with a structured mask layer, allows for etching and deposition of electrically conductive material to create vertical and lateral wiring structures, enabling simultaneous manufacturing of electrical contacts and planarization through chemical-mechanical polishing, thereby reducing defect density and enhancing yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If conventional manufacturing processes are used for shrinking device dimensions, then device scaling is attempted, but defect density increases due to large topographies causing difficulties in layer formation and structuring

Engineering Contradiction:

Improvedevice dimensionVSAvoiddefect density

Core Design Contradiction:

Length of moving objectVSManufacturing precision

Solution Approach 1:

The patent segments the manufacturing process into distinct stages with intermediate planarization steps. The insulation layer is formed first, then etched to create trenches, and finally planarized before subsequent wiring layer formation. This segmentation allows each step to be optimized independently, reducing cumulative defects during scaling.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary planarization of the insulation layer surface before forming subsequent wiring structures. By creating a flat surface in advance, the process eliminates topography-related defects that would otherwise propagate through later manufacturing steps, enabling better control as device dimensions shrink.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If layers are formed on surfaces with large topographies, then device functionality is attempted, but manufacturing difficulty increases leading to high defect density

Engineering Contradiction:

Improvedevice functionalityVSAvoidmanufacturing difficulty

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediate planarization step between trench formation and wiring layer deposition. This intermediate process acts as a mediator that transforms the rough surface created by etching into a flat surface suitable for subsequent layer formation, decoupling the difficulty of trench etching from the quality of wiring layer deposition.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If complex structuring processes are used to create vertical and lateral wiring structures, then electrical connections are achieved, but process complexity increases reducing yield

Engineering Contradiction:

Improveelectrical connectionVSAvoidprocess complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the formation of vertical wiring structures (in trenches) and lateral wiring structures (on surface) into a single integrated process flow. By using the same planarization and deposition steps for both vertical and lateral connections, the process reduces complexity while maintaining reliable electrical connections through both structure types.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces defect density and increases yield by enabling the formation of even surfaces for subsequent manufacturing processes, facilitating the creation of reliable semiconductor devices with improved electrical connections.

Implementation Method 1

etching portions of the second insulation layer uncovered by the structured mask layer and portions of the first insulation layer uncovered by the structured etch stop layer

Methodology Applied

Scientific EffectEtching:

Implementation Method 2

depositing electrically conductive material to form an electrical contact to at least one of the uncovered electrode and the uncovered portion of the semiconductor substrate

Methodology Applied

Scientific EffectDeposition: Deposition (physical)

Implementation Method 3

planarization through chemical-mechanical polishing

Methodology Applied

Scientific EffectChemical-mechanical polishing:

Data Source

PatentUS10403728B2Semiconductor devices having field electrode trenches

Publication Date: 2019.09.03 INFINEON TECH AUSTRIA AG

AI summary

A semiconductor device includes needle-shaped trenches in a semiconductor substrate, each of which includes a field electrode electrically insulated from the semiconductor substrate. Source doping regions and body doping regions of a transistor arrangement are formed in the semiconductor substrate between neighboring ones of the needle-shaped trenches. Gate trenches extend through the source doping regions and the body doping regions. The device further includes a first insulation layer above the semiconductor substrate, an etch stop layer on the first insulation layer, a second insulation layer on the etch stop layer, and an electrically conductive material on the second insulation layer and which contacts the field electrodes, source doping regions and body doping regions through openings which extend through the second insulation layer, etch stop layer and first insulation layer. Islands of the electrically conductive material are surrounded by portions of the second insulation layer above the gate trenches.